3.2.5.2 Vertical Linearity Failure
Expected failure point
IC601 on the DEFL-SUB or peripheral circuits
Check Pin 15 of CN600.
Expected failure point
IC102 on the MAIN PWB or peripheral circuits
NG
OK
Expected failure point
1)
IC401 on the MAIN PWB
2)
IC601, Q603, Q604 or IC603 on the DEFL-SUB PWB
3) Peripheral
circuits
Check how the voltage waveform at Pin 15 of CN600 on the MAIN PWB changes to the
shape of Character C when up and down balance control is carried out for OSM linearity.
Check how the voltage waveform at Pin 15 of CN600 on the MAIN PWB changes to the
shape of Character S when vertical balance control is carried out for OSM linearity.
NG
OK
Check Pins 3 and 8 of CN601.
Check voltage between SW-VLIN1 and SW-VLIN2.
Fv [Hz]
V-Lin-SW1
V-Lin-SW2
50 -
L
L
73 -
H
L
90 -
L
H
125 -
H
H
3-10
Summary of Contents for DPro2070SB
Page 22: ...1 15 Fig 7 The principle of DDCC compensation ...
Page 23: ...1 16 Fig 8 a DDCC adjustment item ...
Page 24: ...1 17 Fig 8 b DDCC adjustment item ...
Page 25: ...1 18 Fig 9 DDCC circuit diagram ...
Page 103: ...4 Wave form 1 POWER 2 CONTROL MAIN 3 DEFL MAIN 4 DEFL SUB COIL DRIVE MAIN 5 VIDEO ...
