1- 4
IC603
R642
R637
IC603
C628
IC601
1
11
VSAW-N
VSAW-P
R652
R658
R650
R651
2
1
6
7
5
3
R645+R646
2
IMID
R647
R648+R649
63
62
Q604
Q603
SW-VLIN1
SW-VLIN2
Fig. 2 Vertical sawtooth waveform output circuit
1.2.4.2 Vertical output amplification circuit
A current proportional to the waveform of the voltage input to IC401 will flow to the vertical deflection coil
(V-DY). R410 reads out the voltage waveform of the vertical deflection current, and then feeds back it to
IC401.
VFLY
-
+
Pump Up
R410
D401
C404
R405
IC451
7
1
6
3
4
5
2
R419+R409
R411
-15.0V
+15.0V
V SAW Input
V-DY
IMID
R406+R418
Fig. 3 Vertical output amplifier circuit
1.2.5 High voltage block
The high voltage block applies PWM control system that controls ON/OFF time of the high voltage
generation FET.
IC701 is the control IC that executes PWM control. The pulse voltage generated at Q701 is boosted at
T701 (FBT) to generate 27kV. To keep the high voltage stably, the feedback voltage from pin 10 of T701
is adopted, the control voltage from pin 56 of microcomputer IC102 is returned to pin 5 of IC701 and the
pulse wise of PWM output is controlled. PWM synchronizes with the horizontal frequency. Trigger pulse
for synchronizing is output from the divided collector pulse of the horizontal deflection output TR Q550,
and is input to pin 8 of IC701.
For adjustment of high voltage value, the voltage of pin 56 of IC102 is adjusted with the adjustment item
HV-ADJ-CAUTION on the OSM menu.
Summary of Contents for DPro2070SB
Page 22: ...1 15 Fig 7 The principle of DDCC compensation ...
Page 23: ...1 16 Fig 8 a DDCC adjustment item ...
Page 24: ...1 17 Fig 8 b DDCC adjustment item ...
Page 25: ...1 18 Fig 9 DDCC circuit diagram ...
Page 103: ...4 Wave form 1 POWER 2 CONTROL MAIN 3 DEFL MAIN 4 DEFL SUB COIL DRIVE MAIN 5 VIDEO ...