3.4.4 High Voltage (HV)Circuit Failure
(Check “3.1 No Raster Generated” before this item)
Expected failure point
The horizontal oscillation/ deflection circuits (See Item3.4.2)
Expected failure point
1) IC701 on the MAIN PWB or 12V line
2) The video circuit (See Item 3.4.5)
Expected failure point
1) Q701, T701 (FBT) or peripheral circuits
2) Video circuit (See Item 3.4.5)
3) The switching power circuit (See Item 3.4.1)
Check the voltage at L701 on the MAIN PWB.
NG
OK
Check the 80V line.
Check the voltage at Pin 10 of IC701 on the MAIN PWB.
NG
OK
Check the voltage at Pin 8 of IC701 on the MAIN PWB.
NG
OK
Check the voltage waveform at the emitter Q702 on the MAIN PWB.
NG
Expected failure point
Q701, IC701 or T701 (FBT) on the MAIN PWB, or peripheral circuit
Check the HV drive pulses
.
Check the AFC pulses.
Check the 12V line.
Check the anode voltage of CRT. Usually, this high voltage is
maintained at about 25kV.
Check the HV.
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Summary of Contents for DPro2070SB
Page 22: ...1 15 Fig 7 The principle of DDCC compensation ...
Page 23: ...1 16 Fig 8 a DDCC adjustment item ...
Page 24: ...1 17 Fig 8 b DDCC adjustment item ...
Page 25: ...1 18 Fig 9 DDCC circuit diagram ...
Page 103: ...4 Wave form 1 POWER 2 CONTROL MAIN 3 DEFL MAIN 4 DEFL SUB COIL DRIVE MAIN 5 VIDEO ...