3.2.4.2 Horizontal Position Failure
(1)Video
Check the H_POSI line.
Expected failure point
Q501, Q502 or Q503 on the MAIN PWB, or peripheral circuits
Expected failure point
IC601 on the DEFL-SUB PWB or peripheral circuits
Confirm that the phase of the voltage waveform at Pin 11 of CN601 on the MAIN PWB
changes when the horizontal position is adjusted with OSM.
OK
NG
(2) Horizontal raster centering (VR5A1) failure
Check the power source voltage for centering.
Expected failure point
L5A1, VR5A1, Q5A1 or Q5A2 on the MAIN PWB, or peripheral circuits
Check voltage between C5A1 and C5A2 on the MAIN PWB. Usually, this
voltage is maintained at 5
±
1V.
OK
Expected failure point
T550, D5A1 or D5A2
NG
3.2.4.3 Vertical Size and Position Failure
Expected failure point
1) IC401
2) The power circuit, D964 or D965 on the power circuit block
NG
Expected failure point
IC401 on the MAIN PWB or peripheral circuits
Expected failure point
IC601 on the DEFL-SUB PWB or peripheral circuits
NG
OK
Check the voltage at Pin 15 of CN600.
Check the voltage at Pin 16
of CN600.
Check the +15 and -15V lines.
Measure voltage at Pin 1 (-15V) and Pin 6 (+15V) of IC401 on the MAIN PWB.
OK
Confirm that the voltage amplitude changes within the range of approx. 2.0 to 3.0 Vp-p
at Pin 15 of CN600 on the MAIN PWB when the vertical size is control with OSM.
Confirm that the voltage amplitude changes within the range of approx. 3.3 to 3.7V at
Pin 16 of CN600 on the MAIN PWB when the vertical position control with OSM.
3-8
Summary of Contents for DPro2070SB
Page 22: ...1 15 Fig 7 The principle of DDCC compensation ...
Page 23: ...1 16 Fig 8 a DDCC adjustment item ...
Page 24: ...1 17 Fig 8 b DDCC adjustment item ...
Page 25: ...1 18 Fig 9 DDCC circuit diagram ...
Page 103: ...4 Wave form 1 POWER 2 CONTROL MAIN 3 DEFL MAIN 4 DEFL SUB COIL DRIVE MAIN 5 VIDEO ...