3.2
.4 Screen Size and Screen Position Failure
3.2.4.1 Horizontal Size Failure
Expected failure point
IC5C0 on the MAIN PWB or peripheral circuits
NG
Measure the waveform at the gate of Q5F1 on the MAIN PWB.
(Approx. 10Vp-p)
Horizontal
period
Expected failure point
Q5F0, Q5F1 or Q550 on the MAIN PWB, or peripheral circuits
Check the waveform at the gate of Q5F1.
NG
OK
Check the voltage at Pin 9 of IC5C0.
Examine the duty factor of the voltage waveform observed at Pin 9 of IC5C0 on the
MAIN PWB and confirm whether it is changed by the adjustment of horizontal size.
OK
Expected failure point
T550 or the horizontal deflection circuit (See Item 3.4.2)
3-7
Summary of Contents for DPro2070SB
Page 22: ...1 15 Fig 7 The principle of DDCC compensation ...
Page 23: ...1 16 Fig 8 a DDCC adjustment item ...
Page 24: ...1 17 Fig 8 b DDCC adjustment item ...
Page 25: ...1 18 Fig 9 DDCC circuit diagram ...
Page 103: ...4 Wave form 1 POWER 2 CONTROL MAIN 3 DEFL MAIN 4 DEFL SUB COIL DRIVE MAIN 5 VIDEO ...