Chapter 4
Register Descriptions
© National Instruments Corporation
4-7
SCXI-1120 User Manual
Hardscan Control Register (HSCR)
The HSCR contains eight bits that control the setup and operation of the hardscan timing
circuitry of Slot 0. To write to the HSCR, follow the procedure given in the Register Writes
section in Chapter 5, Programming, using 13 as the slot number and writing eight bits to the
HSCR. The register will shift in the data present on the MOSI line, bit 7 first, when Slot 13 is
selected by the Slot-Select Register.
Type:
Write-only
Word Size:
8-bit
Bit Map:
7
6
5
4
3
2
1
0
RSVD
FRT
RD
ONCE
HSRS*
LOAD*
SCANCONEN
CLKEN
Bit
Name
Description
7
RSVD
Reserved.
6
FRT
Forced Retransmit – This bit, when clear, causes the scan
list in the FIFO to be reinitialized to the first entry, thus
allowing the scan list to be reprogrammed in two steps
instead of having to rewrite the entire list. When this bit is
set, it has no effect.
5
RD
Read – This bit, when clear, prevents the FIFO from being
read. When set, the FIFO is being read except at the end
of a scan list entry during scanning, when reading is briefly
disabled to advance to the next scan list entry.
4
ONCE
Once – When set, this bit will cause the Hardscan circuitry
to shut down at the end of the scan list circuitry during a
data acquisition. When clear, the circuitry will wrap
around and continue seamlessly with the first scan list entry
after the entry is finished.
3
HSRS*
Hardscan Reset – When clear, this bit causes all the
hardware scanning circuitry, including the FIFO, to be reset
to the power up state. When set, this bit has no effect.
2
LOAD*
Load – This bit, when clear, forces a loading of the Slot 0
sample counter with the output of the FIFO. When set,
this bit has no effect.
1
SCANCONEN
Scan Control Enable – When set, this bit enables the
SCANCON lines. When clear, all SCANCON lines are
disabled (high).
0
CLKEN
Clock Enable – When set, this bit enables TRIG0 as a
clock for the hardscan circuitry. When clear, TRIG0 is
disabled.
