National Instruments NI PXIe-4300, User Manual

Page: 6 / 36

Contents
vi | ni.com
Chapter 3
SC Express Considerations
SC Express Clock and Trigger Signals.............................................................................3-1
PXIe_CLK100 ..........................................................................................................3-1
PXIe_SYNC100........................................................................................................3-1
PXI_CLK10 ..............................................................................................................3-1
PXI Triggers .............................................................................................................3-1
PXI_STAR Trigger...................................................................................................3-2
PXI_STAR Filters.....................................................................................................3-2
PXIe_DSTAR<A..C> ...............................................................................................3-2
Data Transfer Methods .....................................................................................................3-3
Appendix A
NI Services
Figures
Figure 2-1. NI PXIe-4300 AI Source Grounding Diagram......................................2-1
Figure 2-2. NI PXIe-4300 Block Diagram...............................................................2-5
Figure 2-3. NI PXIe-4300 PGIA ..............................................................................2-9
Figure 2-4. Typical Posttriggered DAQ Sequence...................................................2-9
Figure 2-5. Typical Pretriggered DAQ Sequence ....................................................2-10
Figure 2-6. AI Sample Clock and AI Start Trigger..................................................2-12
Figure 2-7. Retriggerable Analog Input ...................................................................2-13
Figure 2-8. Reference Trigger Final Buffer .............................................................2-14
Figure 2-9. Halt (Internal Clock) and Free Running (External Clock) ....................2-15
Figure 2-10. External Clock Reference......................................................................2-17
Figure 2-11. Synchronization Operation ....................................................................2-19
Figure 2-12. Analog Trigger Level ............................................................................2-20
Figure 2-13. Analog Edge Triggering with Hysteresis on Rising Slope....................2-21
Figure 2-14. Analog Edge Triggering with Hysteresis on Falling Slope...................2-21
Figure 2-15. Window Triggering ...............................................................................2-22
Tables
Table 2-1. Front Signal Pin Assignments ..............................................................2-3
Table 2-2. I/O Connector Signal Descriptions........................................................2-4
Table 2-3. NI PXIe-4300 Input Range and Nominal Resolution............................2-6
Table 2-4. Analog Input Rates for NI PXIe-4300 Modules....................................2-10
Table 2-5. Clock Signal Sourcing ...........................................................................2-17
Table 3-1. PXIe_DSTAR Line Descriptions ..........................................................3-2