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Motorola MVME3600 Series Programmer'S Reference Manual Download Page 240

4-14

Computer Group Literature Center Web Site

Universe (VMEbus to PCI) Chip

4

The Configuration Space enables are not the only things enabled after a 
PCI reset. The LSI0 image may also not be disabled by a PCI reset, 
regardless of the enable bit’s Power Up condition. If the image is active at 
the time the reset occurs, it will remain enabled through the reset. 
Additionally, the image is not staying at the same VME or PCI address 
range.

MCG is not sure how many of the Power Up (P/U) Option bits actually get 
latched as the Universe manual indicates they should. At least the EN bit 
in the LSI0_CTL bit is not latched; in our board, its P/U state is disabled 
but is not honored.

The software cannot completely correct this problem, but it can minimize 
it. Two methods are presented:

Method 1:

1. Modify the PCI probe code to disable each PCI device prior to 

writing its configuration space BS registers. This will prevent the 
Universe from being active on the PCI bus while it has a base addr 
of 0.

2. Once the Universe has been assigned a valid PCI Base Address, 

enable register space access and disable the LSI0 slave image by 
clearing the EN bit of the LSI0_CTL register.

Method 2:

The port 92 reset code can be modified to disable the LSI0 image 
prior to propagating the reset. This will cause the LSI0 image to 
come up disabled.

We at MCG understand that both of these methods are awkward, because 
the PCI probe/reset code should not contain any device-specific patches. It 
should only need to follow the probing conventions of the PCI 
specification. However, the only other option appears to be avoidance of 
the LSI0 image altogether.

Tundra engineering describes the problem thus: 

"Following are the most recently discovered bugs which will be 
addressed in Universe 1.1.

Summary of Contents for MVME3600 Series

Page 1: ...MVME3600 4600 Series VME Processor Modules Programmer s Reference Guide V36V46A PG3 August 2001 Edition ...

Page 2: ...ered trademark and PowerPC 604 is a trademark of International Business Machines Corporation and are used by Motorola Inc under license from International Business Machines Corporation AIX is a registered trademark of International Business Machines Corporation SNAPHAT TIMEKEEPER and ZEROPOWER are registered trademarks of STMicroelectronics All other products mentioned in this document are tradema...

Page 3: ...ide the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the po...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constructeur M...

Page 5: ...rts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versio...

Page 6: ...d to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 ...

Page 7: ... 20 Falcon Controlled System Registers 1 25 System Configuration Register SYSCR 1 26 Memory Configuration Register MEMCR 1 27 System External Cache Control Register SXCCR 1 29 CPU Control Register 1 31 ISA Local Resource Bus 1 31 W83C553 PIB Registers 1 31 PC87308VUL Super I O ISASIO Strapping 1 32 NVRAM RTC Watchdog Timer Registers 1 32 Module Configuration and Status Registers 1 33 CPU Configura...

Page 8: ...1 Block Diagram 2 2 Functional Description 2 4 MPC Bus Interface 2 4 MPC Address Mapping 2 4 MPC Slave 2 6 MPC Write Posting 2 8 MPC Master 2 8 MPC Arbiter 2 10 MPC Bus Timer 2 10 PCI Interface 2 10 PCI Address Mapping 2 11 PCI Slave 2 14 PCI Write Posting 2 17 PCI Master 2 17 Generating PCI Cycles 2 20 Endian Conversion 2 25 When MPC Devices are Big Endian 2 25 When MPC Devices are Little Endian ...

Page 9: ...PCI Slave Address 0 1 2 and 3 Registers 2 54 PCI Slave Attribute Offset 0 1 2 and 3 Registers 2 55 CONFIG_ADDRESS Register 2 56 CONFIG_DATA Register 2 58 Raven Interrupt Controller Implementation 2 59 Introduction 2 59 The Raven Interrupt Controller RavenMPIC Features 2 59 Architecture 2 59 CSR s Readability 2 60 Interrupt Source Priority 2 60 Processor s Current Task Priority 2 60 Nesting of Inte...

Page 10: ...riority Register 2 81 Raven Detected Errors Destination Register 2 82 Interprocessor Interrupt Dispatch Registers 2 83 Interrupt Task Priority Registers 2 83 Interrupt Acknowledge Registers 2 84 End of Interrupt Registers 2 85 Programming Notes 2 85 External Interrupt Service 2 85 Reset State 2 86 Operation 2 87 Interprocessor Interrupts 2 87 Dynamically Changing I O Interrupt Configuration 2 87 E...

Page 11: ...ip Defaults 3 21 External Register Set 3 21 CSR Accesses 3 22 Programming Model 3 22 CSR Architecture 3 22 Register Summary 3 28 Detailed Register Bit Descriptions 3 31 Vendor Device Register 3 32 Revision ID General Control Register 3 32 DRAM Attributes Register 3 34 DRAM Base Register 3 36 CLK Frequency Register 3 37 ECC Control Register 3 38 Error Logger Register 3 42 Error_Address Register 3 4...

Page 12: ... 5 Interrupter and Interrupt Handler 4 6 DMA Controller 4 7 Registers Universe Control and Status Registers UCSR 4 7 Universe Register Map 4 8 Universe Chip Problems after a PCI Reset 4 13 Problem Description 4 13 Examples 4 15 Example 1 MVME2600 Series Board Exhibits Problem 4 15 Example 2 MVME3600 Series Board Acts Differently 4 17 Example 3 Universe Chip is Checked at Tundra 4 19 CHAPTER 5 Prog...

Page 13: ...aven s Involvement 5 14 PCI Domain 5 14 PCI SCSI 5 14 PCI Ethernet 5 15 PCI Graphics 5 15 Universe s Involvement 5 15 VMEbus Domain 5 15 ROM Flash Initialization 5 16 APPENDIX A Related Documentation Motorola Computer Group Documents A 1 Manufacturers Documents A 2 Related Specifications A 4 ...

Page 14: ......

Page 15: ...lcon Internal Data Paths Simplified 3 4 Figure 3 3 Overall DRAM Connections 3 5 Figure 3 4 Data Path for Reads from the Falcon Internal CSRs 3 23 Figure 3 5 Data Path for Writes to the Falcon Internal CSRs 3 24 Figure 3 6 Memory Map for Byte Reads to the CSR 3 25 Figure 3 7 Memory Map for Byte Writes to the Internal Register Set and Test SRAM 3 26 Figure 3 8 Memory Map for 4 Byte Reads to the CSR ...

Page 16: ......

Page 17: ...s Slave Map Example 1 25 Table 1 15 System Register Summary 1 25 Table 1 16 Strap Pins Configuration for the PC87308VUL 1 32 Table 1 17 MK48T59 559 Access Registers 1 33 Table 1 18 Module Configuration and Status Registers 1 33 Table 1 19 VME Registers 1 37 Table 1 20 Z8536 Z85230 Access Registers 1 43 Table 1 21 Z8536 CIO Port Pins Assignment 1 44 Table 1 22 Interpretation of MID3 MID0 1 45 Table...

Page 18: ...ock_A B C D Configurations 3 35 Table 3 12 rtest encodings 3 45 Table 3 13 ROM Flash Block A Size Encoding 3 48 Table 3 14 rom_a_rv and rom_b_rv encoding 3 48 Table 3 15 Read Write to ROM Flash 3 49 Table 3 16 ROM Flash Block B Size Encoding 3 51 Table 3 17 Sizing Addresses 3 58 Table 3 18 PowerPC 60x Address to DRAM Address Mappings 3 59 Table 3 19 Syndrome Codes Ordered by Bit in Error 3 60 Tabl...

Page 19: ... MVME3604 5372 300 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and IEEE 1101 front panel for use with MVME761 MVME3604 6342 to MVME3604 6372 300 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and Scanbe front panel for use with MVME712M MVME3604 5442 5462 5472 400 MHz MPC604 64 512MB ECC DRAM 9MB Flash 512KB L2 cache and IEEE 1101 front panel for use with MVME761 MVME3604 6442 646...

Page 20: ...IC Chapter 3 Falcon ECC Memory Controller Chipset provides a functional description and programming model for the Falcon DRAM controller ASIC Chapter 4 Universe VMEbus to PCI Chip gives a general description of the Universe VMEbus interface chip Chapter 5 Programming Details provides programming functions for the different ASIC chips applicable to the MVME3600 4600 series Date Description of Chang...

Page 21: ...ude the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are l...

Page 22: ...ol key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level...

Page 23: ... that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be...

Page 24: ......

Page 25: ...or feature of this chapter Programmable registers in the MVME3600 series and MVME4600 series that reside in ASICs are covered in the chapters on those ASICs Chapter 2 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip covers the Raven processor to PCI bridge Chapter 3 Falcon ECC Memory Controller Chipset covers the Falcon chipset ECC memory controller Chapter 4 Universe VMEbus to PCI ...

Page 26: ...odels based on the MVME3600 4600 series architecture The following table summarizes the major features of the MVME3600 4600 series Table 1 1 MVME3600 4600 Series Features Summary Feature Description Processors Single MVME3600 or dual twin MVME4600 only Supports MPC604 BGA processors only Bus Clock Frequencies up to 66 MHz L2 Cache 512KB Look aside L2 Cache Flash 8MB 64 bit wide with socketed 1MB 1...

Page 27: ...rimary fast SCSI 2 interface 16 bit differential or single ended secondary fast SCSI 2 interface MVME3600 16 bit differential or single ended secondary Ultra SCSI interface MVME4600 AUI or 10BaseT 100BaseTX primary Ethernet interface AUI secondary Ethernet interface MVME3600 10BaseT 100BaseT secondary Ethernet interface MVME4600 1280 x 1024 Graphics Interface One PS 2 Keyboard and one PS 2 Mouse O...

Page 28: ...Literature Center Web Site Board Description and Memory Maps 1 optional synchronous serial ports also reside on the ISA bus The general system block diagrams for the MVME3600 series and the MVME4600 series are shown below ...

Page 29: ...W83C553 ETHERNET DEC21140 SCSI 53C825A VME BRIDGE UNIVERSE BUFFERS AUI 10BT 100BTX VME P2 VME P1 RTC NVRAM WD MK48T559 ISA REGISTERS SUPER I O PC87308 ESCC 85230 CIO Z8536 712 761 P2 I O OPTIONS MOUSE KBD FLOPPY LED PARALLEL SERIAL FRONT PANEL ISA BUS 66MHz MPC604 PROCESSOR BUS GRAPHICS GRAPHICS CL GD54XX VIDEO DRAM DRAM 32MB 64MB SECONDARY ETHERNET AND SCSI PROCESSOR MEMORY MEZZANINE BASE BOARD 6...

Page 30: ... DEC21140 SCSI 53C825A VME BRIDGE UNIVERSE BUFFERS AUI 10BT 100BTX VME P2 VME P1 RTC NVRAM WD MK48T559 ISA REGISTERS SUPER I O PC87308 ESCC 85230 CIO Z8536 712 761 P2 I O OPTIONS MOUSE KBD FLOPPY LED PARALLEL SERIAL FRONT PANEL ISA BUS 66MHz MPC604 PROCESSOR BUS GRAPHICS GRAPHICS CL GD54XX VIDEO DRAM DRAM 64MB SECONDARY ETHERNET AND SCSI PROCESSOR MEMORY MEZZANINE BASE BOARD 64 BIT PMC SLOT Flash ...

Page 31: ...ers timers The MVME3600 4600 series board interfaces to the VMEbus via the P1 and P2 connectors which use the new 5 row 160 pin connectors as specified in the proposed VME64 Extension Standard It also draws 5V 12V and 12V power from the VMEbus backplane through these two connectors The 3 3V supply is regulated onboard from the 5V power Front panel connectors on the MVME3600 4600 series board inclu...

Page 32: ...s D1 through D30 of the 5 row DIN P2 connector J14 pin 31 is connected to P2 pin Z29 and J14 pin 32 is connected to P2 pin Z31 Additional PCI expansion is supported with a 114 pin Mictor connector This connection allows stacking of a carrier board such as a dual PMC carrier board to increase the I O capability Programming Model Memory Maps The following sections describe the memory maps for the MV...

Page 33: ...sh Bank A appears at this range after a reset if the rom_b_rv control bit in the Falcon chip is cleared and the rom_a_rv control bit is set If the rom_b_rv control bit is set then this address range maps to ROM Flash Bank B Table 1 2 Default Processor Memory Map Processor Address Size Definition Notes Start End 0000 0000 7FFF FFFF 2G Not mapped 8000 0000 8001 FFFF 128K PCI ISA I O Space 1 8002 000...

Page 34: ...00 0000 FCFF FFFF 3G 48M PCI Memory Space 4000 0000 to FCFF FFFF 3 4 8 FD00 0000 FDFF FFFF 16M Zero Based PCI ISA Memory Space mapped to 00000000 to 00FFFFFF 3 8 FE00 0000 FE7F FFFF 8M Zero Based PCI ISA I O Space mapped to 00000000 to 007FFFFF 3 5 8 FE80 0000 FEF7 FFFF 7 5M Reserved FEF8 0000 FEF8 FFFF 64K Falcon Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF 64K Raven Registers ...

Page 35: ...ntrol bit is set If the rom_b_rv control bit is set then this address range maps to ROM Flash Bank B 8 This range can be mapped to the VMEbus by programming the Universe ASIC accordingly The map shown is the recommended setting which uses the Special PCI Slave Image and two of the four programmable PCI Slave Images 9 The only method of generating a PCI Interrupt Acknowledge cycle 8259 IACK is to p...

Page 36: ... End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 8000 0000 BFFF FFFF 1G Zero Based PCI I O Space 0000 0000 3FFFF FFFF 2 C000 0000 FCFF FFFF 1G 48M Zero Based PCI ISA Memory Space 0000 0000 3CFFFFFF 2 5 FD00 0000 FEF7 FFFF 40 5M Reserved FEF8 0000 FEF8 FFFF 64K Falcon Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF 64K Raven Registers Table 1 10 on page 1 17 has MPIC 6...

Page 37: ... to the VMEbus by programming the Universe ASIC accordingly 6 The only method of generating a PCI Interrupt Acknowledge cycle 8259 IACK is to perform a read access to the Raven s PIACK register at 0xFEFF0030 The following table shows the programmed values for the associated Raven MPC registers for the processor PREP memory map Table 1 6 Raven MPC Register Values for PREP Memory Map Address Registe...

Page 38: ...niverse ASIC have flexible programming Map Decoder registers to customize the system to fit many different applications Default PCI Memory Map After a reset the Raven ASIC and the Universe ASIC turn all the PCI slave map decoders off Software must program the appropriate map decoders for a specific environment PCI CHRP Memory Map The following table shows a PCI memory map of the MVME3600 4600 seri...

Page 39: ...sters for the PCI CHRP memory map F900 0000 F9FE FFFF 16M 64K VMEbus A24 D32 Super Data 4 F9FF 0000 F9FF FFFF 64K VMEbus A16 D32 Super Data 4 FA00 0000 FAFE FFFF 16M 64K VMEbus A24 D16 User Program 4 FAFF 0000 FAFF FFFF 64K VMEbus A16 D16 User Program 4 FB00 0000 FBFE FFFF 16M 64K VMEbus A24 D32 User Data 4 FBFF 0000 FBFF FFFF 64K VMEbus A16 D32 User Data 4 FC00 0000 FC03 FFFF 256K RavenMPIC 1 FC0...

Page 40: ...000 FC00 0000 80 PSADD0 0000 3FFF 0100 3FFF 84 PSOFF0 PSATT0 0000 00FX 0000 00FX 88 PSADD1 0000 0000 FD00 FDFF 8C PSOFF1 PSATT1 0000 0000 0000 00FX 90 PSADD2 0000 0000 0000 0000 94 PSOFF2 PSATT2 0000 0000 0000 0000 98 PSADD3 0000 0000 0000 0000 9C PSOFF3 PSATT3 0000 0000 0000 0000 Table 1 9 Universe PCI Register Values for CHRP Memory Map Configuration Address Offset Configuration Register Name Re...

Page 41: ... SLSI C0A053F8 Table 1 10 PCI PREP Memory Map PCI Address Size Definition Notes Start End 0000 0000 00FF FFFF 16M PCI ISA Memory Space 0100 0000 2FFF FFFF 752M VMEbus A32 D32 Super Program 3 3000 0000 37FF FFFF 128M VMEbus A32 D16 Super Program 3 3800 0000 38FE FFFF 16M 64K VMEbus A24 D16 Super Program 4 38FF 0000 38FF FFFF 64K VMEbus A16 D16 Super Program 4 3900 0000 39FE FFFF 16M 64K VMEbus A24 ...

Page 42: ...The following table shows the programmed values for the associated Raven PCI registers for the PREP compatible memory map 3A00 0000 3AFE FFFF 16M 64K VMEbus A24 D16 User Program 4 3AFF 0000 3AFF FFFF 64K VMEbus A16 D16 User Program 4 3B00 0000 3BFE FFFF 16M 64K VMEbus A24 D32 User Data 4 3BFF 0000 3BFF FFFF 64K VMEbus A16 D32 User Data 4 3C00 0000 7FFF FFFF 1G 64M PCI Memory Space 8000 0000 FBFF F...

Page 43: ...MPIC MBASE FC00 0000 80 PSADD0 8000 FBFF 84 PSOFF0 PSATT0 8000 00FX 88 PSADD1 0000 0000 8C PSOFF1 PSATT1 0000 0000 90 PSADD2 0000 0000 94 PSOFF2 PSATT2 0000 0000 98 PSADD3 0000 0000 9C PSOFF3 PSATT3 0000 0000 Table 1 12 Universe PCI Register Values for PREP Memory Map Configuration Address Offset Configuration Register Name Register Value 100 LSI0_CTL C082 5100 104 LSI0_BS 0100 0000 108 LSI0_BD 30...

Page 44: ...d mapping is shown in Processor Memory Maps on page 1 8 The following figure illustrates how the VMEbus master mapping is accomplished 128 LSI2_CTL 0000 0000 12C LSI2_BS XXXX XXXX 130 LSI2_BD XXXX XXXX 134 LSI2_TO XXXX XXXX 13C LSI3_CTL 0000 0000 140 LSI3_BS XXXX XXXX 144 LSI3_BD XXXX XXXX 148 LSI3_TO XXXX XXXX 188 SLSI C0A05338 Table 1 12 Universe PCI Register Values for PREP Memory Map Configura...

Page 45: ... Figure 1 3 VMEbus Master Mapping VMEBUS 11553 00 9609 VME A24 VME A16 VME A24 VME A16 VME A24 VME A16 VME A24 VME A16 PROGRAMMABLE SPACE PCI MEMORY PROCESSOR PCI MEMORY SPACE PCI ISA MEMORY SPACE PCI I O SPACE MPC RESOURCES NOTE 1 NOTE 1 NOTE 2 NOTE 3 ONBOARD MEMORY ...

Page 46: ...p The four programmable VME Slave Images in the Universe ASIC allow other VMEbus masters to get to any devices on the MVME3600 4600 series The combination of the four Universe VME Slave Images and the four Raven PCI Slave Decoders offers a lot of flexibility for mapping the system resources as seen from the VMEbus In most applications the VMEbus only needs to see the system memory and perhaps the ...

Page 47: ...tes 1 Programmable mapping via the four VME Slave Images in the Universe ASIC 2 Programmable mapping via PCI Slave Images in the Raven ASIC 3 Fixed mapping via the PIB device 1896 9609 PCI Memory NOTE 2 NOTE 1 Software INT Registers Processor ISA Space Onboard Memory VMEbus NOTE 1 PCI I O Space NOTE 3 ...

Page 48: ...on Register Name Register Value CHRP Register Value PREP F00 VSI0_CTL C0F2 0001 C0F2 0001 F04 VSI0_BS 4000 0000 4000 0000 F08 VSI0_BD 4000 1000 4000 1000 F0C VSI0_TO C000 1000 C000 1000 F14 VSI1_CTL E0F2 00C0 E0F2 00C0 F18 VSI1_BS 1000 0000 1000 0000 F1C VSI1_BD 2000 0000 2000 0000 F20 VSI1_TO F000 0000 7000 0000 F28 VSI2_CTL 0000 0000 0000 0000 F2C VSI2_BS XXXX XXXX XXXX XXXX F30 VSI2_BD XXXX XXX...

Page 49: ...hese system registers in detail Table 1 14 VMEbus Slave Map Example VMEbus Address Size CHRP Map PREP Map Range Mode 4000 0000 4000 0FFF A32 U S P D D08 16 32 4K PCI ISA I O Space 0000 1000 0000 1FFF PCI ISA I O Space 0000 1000 0000 1FFF 1000 0000 1FFF FFFF A32 U S P D D08 16 32 64 RMW 256M PCI ISA Memory Space On board DRAM 0000 0000 0FFF FFFF PCI ISA Memory Space On board DRAM 8000 0000 8FFF FFF...

Page 50: ... system configuration so that the software may appropriately handle any software visible differences For the MVME3600 series and the MVME4600 series this field returns a value of FE SYSCLK System Clock Speed This field relays the system clock speed and the PCI clock speed information as follows SYSXC System External Cache Size This field reflects size of the look aside cache on the system bus REG ...

Page 51: ... and stored in this Memory Configuration Register to provide some information about the system memory Configuration is accomplished with external pull down resistors This 32 bit read only register is defined as follows SYSXC Value External Look aside Cache Size 0b0000 to 0b1011 Reserved 0b1100 1M 0b1101 512K 0b1110 256K 0b1111 None P0 1STAT Value Processor 0 1 Present External In line Cache Size 0...

Page 52: ...eflect the combined status of the four blocks of DRAM Initialization software uses this information to program the ram_spd0 and ram_spd1 control bits in the Falcon s Chip Revision Register REG Memory Configuration Register FEF80404 BIT 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FIELD M_FREF M_SPD0 M_SPD1 R_A_TYP0 R_A_TYP1 R_A_TYP2 R_B_TYP0 R_B_T...

Page 53: ...nes of the upper Falcon device This 8 bit register is defined as follows SXC_DIS_ System External Cache Enable When this bit is cleared it disables this cache from responding to any bus cycles SXC_FLSH_ System External Cache Flush When this bit is pulsed true for at least 8 clock periods it causes the system external ROM_A B_TYP 0 2 ROM Flash Type 0b000 to 0b101 Reserved 0b110 Intel 16 bit wide Fl...

Page 54: ...ot wait that long to become MPC bus master SXC_RST_ System External Cache Reset When this bit is cleared it invalidates all tags and holds the cache in a reset condition There is a bug in Glance It really does not hold the chip in a reset condition The tag invalidate still works okay though SXC_MI_ System External Cache Miss Inhibit When this bit is cleared it prevents line fills on cache misses W...

Page 55: ... LEND bit in the Raven for little endian mode P0 1_TBEN Processor 0 1 Time Base Enable When this bit is cleared the TBEN pin of Processor 0 1 will be driven low ISA Local Resource Bus W83C553 PIB Registers The PIB contains ISA Bridge I O registers for various functions These registers are actually accessible from the PCI bus Refer to the W83C553 Data Book for details REG CPU Control Register FEF88...

Page 56: ...es the MVME3600 4600 series with 8K of non volatile SRAM a time of day clock and a watchdog timer Accesses to the MK48T59 559 are accomplished via three registers The NVRAM RTC Address Strobe 0 Register the NVRAM RTC Address Strobe 1 Register and the NVRAM RTC Data Port Register The NVRAM RTC Address Strobe 0 Register latches the lower 8 bits of the address and the NVRAM RTC Address Strobe 1 Regis...

Page 57: ...ditional details and programming information Module Configuration and Status Registers Four registers provide the configuration and status information about the board These registers are listed in the following table Table 1 17 MK48T59 559 Access Registers PCI I O Address Function 0000 0074 NVRAM RTC Address Strobe 0 A7 A0 0000 0075 NVRAM RTC Address Strobe 1 A15 A8 0000 0077 NVRAM RTC Data Regist...

Page 58: ...e used to obtain information about the overall system CPUTYPE CPU Type This field will always read as E for the MVME3600 4600 series The System Configuration Register should be used for additional information Base Module Feature Register The Base Module Feature Register is an 8 bit register providing the configuration information about the MVME3600 MVME4600 VME Processor Module This read only regi...

Page 59: ...ent If set there is no VMEbus interface If cleared VMEbus interface is supported GFXP_ Graphics Present If set there is no on board Graphics interface If cleared there is an on board graphics capability LANP_ Ethernet Present If set there is no Ethernet transceiver interface If cleared there is on board Ethernet support SCSIP_ SCSI Present If set there is no on board SCSI interface If cleared on b...

Page 60: ...adecimal value of the most significant digit DIG2 3 0 Hexadecimal value of the third significant digit RESET N A BASE_TYPE Value Base Module Type 0 to F9 Reserved FA Reserved Special FB MVME2600 with MVME712M I O FC MVME2600 with MVME761 I O FD MVME3600 4600 with MVME712M I O FE MVME3600 4600 with MVME761 I O FF MVME1600 001 or MVME1600 011 REG 7 Segment Display Register Offset 08C0 BIT SD15 SD14 ...

Page 61: ... to be accessible from the VMEbus the Universe ASIC must be programmed to map the VMEbus Slave Image 0 into the appropriate PCI I O address range Refer to VMEbus Slave Map on page 1 22 for additional details These registers are described in the following subsections Table 1 19 VME Registers PCI I O Address Function 0000 1000 LM SIG Control Register 0000 1001 LM SIG Status Register 0000 1002 VMEbus...

Page 62: ... SIG1 status bit SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit SET_LM1 Writing a 1 to this bit will set the LM1 status bit SET_LM0 Writing a 1 to this bit will set the LM0 status bit CLR_SIG1Writing a 1 to this bit will clear the SIG1 status bit CLR_SIG0Writing a 1 to this bit will clear the SIG0 status bit CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit CLR_LM0 Writi...

Page 63: ...EN_SIG0 When the EN_SIG0 bit is set a LM SIG Interrupt 0 is generated if the SIG0 bit is asserted EN_LM1 When the EN_LM1 bit is set a LM SIG Interrupt 1 is generated and the LM1 bit is asserted EN_LM0 When the EN_LM0 bit is set a LM SIG Interrupt 0 is generated and the LM0 bit is asserted SIG1 SIG1 status bit This bit can only be set by the SET_LM1 control bit It can only be cleared by a reset or ...

Page 64: ...r The Location Monitor Upper Base Address Register is an 8 bit register located at ISA I O address x1002 The Universe ASIC is programmed so that this register can be accessed from the VMEbus to provide VMEbus location monitor function VA 15 8 Upper Base Address for the location monitor function Location Monitor Lower Base Address Register The Location Monitor Lower Base Address Register is an 8 bi...

Page 65: ...f the new value has the most significant bit cleared When bit 7 is high this register will not latch in the new value if the new value has the most significant bit set Semaphore Register 2 The Semaphore Register 2 is an 8 bit register located at ISA I O address x1005 The Universe ASIC is programmed so that this register can be accessible from the VMEbus This register can only be updated if bit 7 i...

Page 66: ... Register VGAR The VME Geographical Address Register is an 8 bit read only register located at ISA I O address x1006 This register reflects the states of the geographical address pins at the 5 row 160 pin P1 connector REG Semaphore Register 2 Offset 1005 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD SEM2 OPER R W RESET 0 0 0 0 0 0 0 0 REG VME Geographical Address Register Offset 1006 BIT SD7 SD6 SD5 S...

Page 67: ...formation Z8536 Z85230 Registers Accesses to the Z8536 CIO and the Z85230 ESCC are accomplished via Port Control and Port Data Registers The PCLK to the Z8536 is 5 MHz Also a Pseudo IACK Register is also defined to retrieve interrupt vectors from these devices The Z8536 CIO has higher priority than the Z85230 ESCC in the interrupt daisy chain The following table lists the registers associated with...

Page 68: ... IDREQ_ 0 IDREQ_ 0 MODSEL 0 Port 3 ID Select IDREQ_ 0 MODSEL 1 Port 4 ID Select PA4 RLB3_ Output Port 3 Remote Loopback PA5 DTR3_ Output Port 3 Data Terminal Ready PA6 BRDFAIL Output Board Fail When set will cause FAIL LED to be lit PA7 IDREQ_ Output Module ID Request low true PB0 TM4_ MID2 Input Port 4 Test Mode when IDREQ_ 1 Module ID Bit 2 when IDREQ_ 0 PB1 DSR4_ MID3 Input Port 4 Data Set Read...

Page 69: ...2 Reserved I O Reserved PC3 Reserved I O Table 1 22 Interpretation of MID3 MID0 IDREQ_ LLB3_ MODSEL MID3 MID2 MID1 MID0 Serial Module Type Module Assembly Number 1 X X X X X Invalid module ID 0 0 0 0 0 0 Module 3 EIA232 DCE 01 W3876B01 0 0 0 0 0 1 Module 3 EIA232 DTE 01 W3877B01 0 0 0 0 1 0 Module 3 EIA530 DCE 01 W3878B01 0 0 0 0 1 1 Module 3 EIA530 DTE 01 W3879B01 0 0 1 1 1 1 Module 3 Not Install...

Page 70: ...ting time should be about 4 microseconds because the sampling rate is about 1 6 microsecond with a 10 MHz MXCLK clock ISA DMA Channels There are seven ISA DMA channels in the PIB Channels 0 through 3 support only 8 bit DMA devices while Channels 5 through 7 support only 16 bit DMA devices These DMA channels are assigned as follows 0 1 0 0 1 1 Module 4 EIA530 DTE 01 W3879B01 0 1 1 1 1 1 Module 4 No...

Page 71: ...3 PIB DMA Channel Assignments PIB Priority PIB Label Controller DMA Assignment Highest Channel 0 DMA1 Serial Port 3 Receiver Z85230 Port A Rx Channel 1 Serial Port 3 Transmitter Z85230 Port A Tx Channel 2 Floppy Drive Controller Channel 3 Parallel Port Channel 4 DMA2 Not available Cascaded from DMA1 Channel 5 Serial Port 4 Receiver Z85230 Port B Rx Channel 6 Serial Port 4 Transmitter Z85230 Port B...

Page 72: ......

Page 73: ... clock Summary of Features The following table summarizes the characteristics of the Raven PCI Host Bridge Function Features MPC Bus Interface Direct interface to MPC603 or MPC604 processors 64 bit data bus 32 bit address bus Four independent software programmable slave map decoders Multi level write post FIFO for writes to PCI Support for MPC bus clock speeds up to 66 MHz Selectable big or little...

Page 74: ...nterrupt Controller MPIC compliant Support for 16 external interrupt sources and two processors Multiprocessor interrupt control allowing any interrupt source to be directed to either processor Multilevel cross processor interrupt control for multiprocessor synchronization Four 31 bit tick timers Two 64 bit general purpose registers for cross processor messaging Function Features ...

Page 75: ...3 2 Figure 2 1 Raven Block Diagram 1914 9702 Data Path B Mux FIFO Endian Mux FIFO Endian Data Path A PCI Regs MPIC PCI Dec Mux Reg Mux Reg PCI Slave MPC Slave Reg Reg MPC Dec PCIADIN PCI Master Mux PCI MPC Master MPC Regs Raven PCI Bus MPC Bus Mux MPC MPCADIN ...

Page 76: ...some restrictions on access to the RavenMPIC the PCI Registers and the MPC Registers The RavenMPIC and the PCI Registers are only accessible to PCI originated transactions The MPC Registers are only accessible to MPC originated transactions MPC Bus Interface The MPC Bus Interface is designed to be coupled directly to up to two MPC603 or MPC604 microprocessors as well as a memory cache subsystem It...

Page 77: ...n represent There is a lower limit of a minimum of 64KB due to the resolution of the address compare logic For each map there is an associated set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the PCI transfer characteristics MPC Bus Address 8 0 8 0 1 2 3 4 31 16 15 0 MSADDx Register 7 0 8 0 9 0 0 0 31 16 15 0 and Decode is ...

Page 78: ...re should be taken to assure that all programmable decoders decode unique address ranges since overlapping address ranges will lead to undefined operation MPC Slave The MPC slave provides the interface between the MPC bus and the Raven FIFOs The MPC slave is responsible for tracking and maintaining coherency to the 60x processor bus protocol The MPC slave divides MPC command types into three categ...

Page 79: ...r Only Kill Block 01100 Addr Only EIEIO 10000 Addr Only ECOWX 10100 No Response TLB Invalidate 11000 Addr Only ECIWX 11100 No Response LWARX 00001 Addr Only STWCX 00101 Addr Only TLBSYNC 01001 Addr Only ICBI 01101 Addr Only Reserved 1XX01 No Response Write with flush 00010 Write Write with kill 00110 Write Read 01010 Read Read with intent to modify 01110 Read Write with flush atomic 10010 Write Re...

Page 80: ...gun to assure that all transfers are completed in the order issued All write posted transfers will also be completed before any access to the Raven s registers is begun MPC Master The MPC master will attempt to move data using burst transfers wherever possible A 64 bit by 16 entry FIFO is used to hold data between the PCI slave and the MPC master to ensure that optimum data throughput is maintaine...

Page 81: ... is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit Table 2 2 shows the relationship between PCI command codes and the INV bit Table 2 2 MPC Transfer Types The MPC master incorporates an optional operating mode called Bus Hog When Bus Hog is enabled the MPC master will continually request the MPC bus for the entire duration of each PCI transf...

Page 82: ...ecover from a lock up condition caused when no slave responds to the transfer request The time out length of the bus timer is determined by the MBT field in the Global Control Status Register The bus timer starts ticking at the beginning of an address transfer TS asserted and if the address transfer is not terminated AACK asserted before the time out period has passed the Raven will assert the MAT...

Page 83: ...is fully compliant with the PCI Local Bus Specification 2 0 definition for configuration space There are two base registers within the standard 64 byte header that are used to control the mapping of RavenMPIC One register is dedicated to mapping RavenMPIC into PCI I O space and the other register is dedicated to mapping RavenMPIC into PCI Memory space The mapping of MPC address space is handled by...

Page 84: ...ce a map decoder can represent There is a lower limit of a minimum of 64KB due to the resolution of the address compare logic For each map there is an independent set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the MPC bus transfer characteristics PCI Bus Address 8 0 8 0 1 2 3 4 0 15 16 31 PSADDx Register 7 0 8 0 9 0 0 0 0 1...

Page 85: ...xample of this is show below Figure 2 5 PCI to MPC Address Translation All Raven address decoders are prioritized so that programming multiple decoders to respond to the same address is not a problem When the PCI address falls into the range of more than one decoder only the highest priority one will respond The decoders are prioritized as shown below Decoder Priority PCI Slave 0 highest PCI Slave...

Page 86: ...re room in the FIFO The slave will not initiate a disconnect If the write transaction is compelled the slave will hold off the master with wait states while each beat of data is being transferred The slave will acknowledge the completion of the transfer only after the data transfer has successfully completed on the MPC bus If a read transaction is being performed within an address space marked for...

Page 87: ...e slave will return an entire word of data regardless of the byte enables During I O read cycles the slave will perform integrity checking of the byte enables against the address being presented and assert SERR in the event there is an error Table 2 3 PCI Slave Response Command Types Command Type Slave Response Interrupt Acknowledge No Special Cycle No I O Read Yes I O Write Yes Reserved No Reserv...

Page 88: ...rm a transaction with byte enable holes Fast Back to Back Transactions The PCI slave supports both of the fundamental target requirements for fast back to back transactions The PCI slave meets the first criteria of being able to successfully track the state of the PCI bus without the existence of an IDLE state between transactions The second criteria associate with signal turn around timing is met...

Page 89: ...ion has completed If during a transaction the write post buffer gets full subsequent PCI data transfers will be delayed TRDY will not be asserted until the Raven has removed some data from the FIFO Under normal conditions the Raven should be able to empty the FIFO faster than the PCI bus can fill it PCI Configuration cycles intended for internal Raven registers will also be delayed if Raven is bus...

Page 90: ...ported since it is conceivable that bursting could happen For example nothing prevents the processor from loading up a cache line with PCI write data and manually flushing the cache line The following paragraphs identify some associations between the operation of the PCI master and the PCI 2 0 Local Bus Specification requirements Command Types The PCI Command Codes generated by the PCI master depe...

Page 91: ...on is aborted due to a Raven detected bridge lock The same happens if the target responds with a disconnect and there is still data to be transferred If the PCI master detects a target abort during a read any untransferred read data will be filled with ones If the PCI master detects a target abort during a write any untransferred portions of data will be dropped The same rule applies if the PCI ma...

Page 92: ... to back transactions Arbitration Latency Because a bulk of the transactions are limited to single beat transfers on PCI the PCI master does not implement a Master Latency Timer Exclusive Access The PCI master is not able to initiate exclusive access transactions Address Data Stepping The PCI master does not participate in the Address Data Stepping protocol Parity The PCI master supports address p...

Page 93: ...bes two approaches for handling PCI I O addressing contiguous or spread address modes When the MEM bit is cleared the IOM bit is used to select between these two modes whenever a PCI I O cycle is to be performed The Raven will perform contiguous I O addressing when the MEM bit is clear and the IOM bit is clear The Raven will take the MPC address apply the offset specified in the MSOFFx register an...

Page 94: ...sfer of four bytes starting at address 80000011 is considered an invalid transfer since it crosses the natural word boundary at address 80000013 80000014 Generating PCI Configuration Cycles The Raven uses configuration mechanism 1 as defined in the PCI Local Bus Specification 2 0 to generate configuration cycles Please refer to this specification for a complete description of this function Configu...

Page 95: ...ace The Raven address decode logic has been designed such that MSADD3 and MSOFF3 must be used for mapping to PCI Configuration consequently I O space The MSADD3 MSOFF3 register group is initialized at reset to allow PCI I O access starting at address 80000000 The powerup location for example little endian disabled of the CONFIG_ADDRESS register is 80000CF8 and the CONFIG_DATA register is located a...

Page 96: ... field The Raven will detect a non zero field and convert the transaction to a Type 1 Configuration cycle Generating PCI Special Cycles Raven supports the method stated in PCI Local Bus Specification 2 0 using Configuration Mechanism 1 to generate special cycles To prime Raven for a special cycle the host processor must write a 32 bit value to the CONFIG_ADDRESS register The contents of the write ...

Page 97: ...ormation obtained from the PCI bus as read data Endian Conversion The Raven supports both big and little endian data formats Since the PCI bus is inherently little endian conversion is necessary if all MPC devices are configured for big endian operation The Raven may be programmed to perform the endian conversion described below When MPC Devices are Big Endian When all MPC devices are operating in...

Page 98: ... passed on to the PCI bus Note that no data swapping is performed Address modification happens to the originating address regardless of whether the transaction originates from the PCI bus 1916 9610 DH07 00 DH15 08 DH23 16 DH31 24 DL07 00 DL15 08 DL23 16 DL31 24 D0 D1 D2 D3 D4 D5 D6 D7 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 AD63 56 AD55 48 AD47 40 AD39 32 AD31 24 AD23 16 AD15 08 AD07 00 DH...

Page 99: ...igned PCI transfers into multiple aligned PCI transfers into multiple aligned transfers on the MPC bus Raven Registers The Raven registers are not sensitive to changes in big endian and little endian mode With respect to the MPC bus but not always the address internal to the processor the MPC registers are always represented in big endian mode This means that the processor s internal view of the M...

Page 100: ... PIACK cycle is undefined therefore address modification during little endian mode is not an issue Error Handling The Raven will be capable of detecting and reporting the following errors to one or more MPC masters MPC address bus time out PCI master signalled master abort PCI master received target abort PCI parity error PCI system error Each of these error conditions will cause an error status b...

Page 101: ...r or associated with masters other than processor 0 1 or 2 the DFLT bit is used One example of an error condition which cannot be associated with a particular MPC master would be a PCI system error Transaction Ordering Raven supports transaction ordering with an optional FIFO flushing option The FLBRD Flush Before Read bit within the GCSR register controls the flushing of PCI write posted data whe...

Page 102: ...onfiguration Registers reside in PCI configuration space They are accessible from the MPC bus through the Raven The MPC Registers are described first the PCI Configuration Registers are described next A complete discussion of the RavenMPIC registers can be found later in this chapter The following conventions are used in the Raven register charts R Read Only field R W Read Write field S Writing a ...

Page 103: ...8 FEFF003C FEFF0040 MSADD0 FEFF0044 MSOFF0 MSATT0 FEFF0048 MSADD1 FEFF004C MSOFF1 MSATT1 FEFF0050 MSADD2 FEFF0054 MSOFF2 MSATT2 FEFF0058 MSADD3 FEFF005C MSOFF3 MSATT3 FEFF0060 FEFF0064 FFEF0068 FEFF006C FEFF0070 GPREG0 Upper Table 2 6 Raven MPC Register Map Continued Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 ...

Page 104: ... Registers DEVID Device ID This register identifies this particular device The Raven will always return 4801 This register is duplicated in the PCI Configuration Registers FEFF0074 GPREG0 Lower FEFF0078 GPREG1 Upper FEFF007C GPREG1 Lower Address FEFF0000 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name VENID DEVID Operation R R Re...

Page 105: ... swapped as described in When MPC Devices are Big Endian on page 2 25 Address FEFF0004 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name REVID Operation R R R R Reset 00 02 00 00 Address FEFF0008 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name GCSR FEAT LEND BHOG ...

Page 106: ...ly request the MPC bus for the entire duration of each PCI transfer If Bus Hog is not enabled the MPC master will request the bus in a normal manner Please refer to MPC Master on page 2 8 for more information MBTx MPC Bus Time out This field specifies the MPC bus time out length The time out length is encoded as follows P64 64 bit PCI Mode Enable This bit will always be set indicating the Raven is...

Page 107: ...m software MPC Arbiter Control Register This register is not used by the MVME3600 4600 MID Current MPC Data Bus Master 00 device on ABG0 01 device on ABG1 10 device on ABG2 11 Raven Address FEFF000C Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name MARB BREN2 BREN1 BREN0 PKEN PKMD GLMD BAMD DEFM1 DEFM0 Operation R R R R R R R R W R...

Page 108: ...s register should be written with the value of BE indicating a 66 MHz MPC bus MPC Error Enable Register Address FEFF0010 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name PADJ Operation R R R R W Reset 00 00 00 B4 Address FEFF0020 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 ...

Page 109: ...CI Parity Error Machine Check Enable When this bit is set the PERR bit in the MERST register will be used to assert the MCHK output to bus master 0 When this bit is clear MCHK will not be asserted SERRM PCI System Error Machine Check Enable When this bit is set the SERR bit in the MERST register will be used to assert the MCHK output to bus master 0 When this bit is clear MCHK will not be asserted...

Page 110: ...ear no interrupt will be asserted SERRI PCI System Error Interrupt Enable When this bit is set the PERR bit in the MERST register will be used to assert an interrupt through the OpenPIC interrupt controller When this bit is clear no interrupt will be asserted SMAI PCI Master Signalled Master Abort Interrupt Enable When this bit is set the SMA bit in the MERST register will be used to assert an int...

Page 111: ...bit in the MEREN register is set the assertion of this bit will assert an interrupt through the OpenPIC interrupt controller PERR PCI Parity Error This bit is set when the PCI PERR pin is asserted It may be cleared by writing a 1 to it writing a 0 to it has no effect When the PERRM bit in the MEREN register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit ...

Page 112: ...transaction It may be cleared by writing a 1 to it writing a 0 to it has no effect When the SMAM bit in the MEREN register is set the assertion of this bit will assert MCHK to the master designated by the MID field in the MERAT register When the SMAI bit in the MEREN register is set the assertion of this bit will assert an interrupt through the OpenPIC interrupt controller RTA PCI Master Received ...

Page 113: ...RR or SERR bits are set in the MERST register the contents of the MERAT register are zero If the MATO bit is set the register is defined by the following figure Address FEFF0028 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name MERAD Operation R Reset 00000000 Address FEFF002C Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7...

Page 114: ...ccurred If the SMA or RTA bits are set the register is defined by the following figure WP Write Post Completion This bit is set when the PCI master detects an error while completing a write post transfer MIDx MPC Master ID This field contains the ID of the MPC master which originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register COMMx P...

Page 115: ...nable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the Raven will present the resulting vector information obtained from the PCI bus as read data MPC Slave Address 0 1 and 2 Registers Address FEFF0030 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name PIACK Oper...

Page 116: ...he upper 16 bits of the incoming MPC address MPC Slave Address 3 Register MSADD3 MSOFF3 and MSATT3 represent the only register group which can be used to initiate access to the PCI CONFIG_ADDRESS 80000CF8 and CONFIG_DATA 80000CFC registers Note that this implies that MSxxx3 also represents the generation of PCI Special Cycles The power up default values of MSADD3 MSOFF3 and MSATT3 are set to allow...

Page 117: ...ress MPC Slave Offset Attribute 0 1 and 2 Registers MSOFFx MPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the MPC address to determine the PCI address used for transfers from the MPC bus to PCI This offset allows PCI resources to reside at addresses that would not normally be visible from the MPC bus REN Read Enable If set the corresponding MPC slave ...

Page 118: ...ed in Generating PCI Cycles on page 2 20 When clear the corresponding MPC slave will generate PCI I O cycles using contiguous addressing This field only has meaning when the MEM bit is clear MPC Slave Offset Attribute 3 Registers MSOFF3 MPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the MPC address to determine the PCI address used for transfers from ...

Page 119: ...ycles using contiguous addressing General Purpose Registers These general purpose read write registers are provided for inter process message passing or general purpose storage They do not control any hardware PCI Registers The PCI Configuration Registers are compliant with the configuration register set described in the PCI Local Bus Specification Revision 2 0 The CONFIG_ADDRESS and CONFIG_DATA r...

Page 120: ...rs will be completed normally and a data value of 0 returned The Raven PCI Configuration Register map is shown in Table 2 7 The Raven PCI I O Register map is shown in Table 2 8 Table 2 7 Raven PCI Configuration Register Map 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Bit DEVID VENID 00 PSTAT PCOMM 04 CLASS REVID 08 0C IOBASE 10 MEMBAS...

Page 121: ...register is duplicated in the MPC Registers DEVID Device ID This register identifies the particular device The Raven will always return 4801 This register is duplicated in the MPC Registers 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Bit CONFIG_ADDRESS CF8 CONFIG_DATA CFC Offset 00 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1...

Page 122: ...ck parity on all PCI transfers If cleared the Raven will ignore any parity errors that it detects and continue normal operation SERR System Error Enable This bit enables the SERR output pin If clear the Raven will never drive SERR If set the Raven will drive SERR active when a system error is detected FAST Fast Back to Back Capable This bit indicates that the Raven is capable of accepting fast bac...

Page 123: ...t It is cleared by writing it to 1 writing a 0 has no effect RCVTA Received Target Abort This bit is set by the PCI master whenever its transaction is terminated by a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVMA Received Master Abort This bit is set by the PCI master whenever its transaction except for Special Cycles is terminated by a master abort It is cleared by...

Page 124: ...6 PCI Bridge Device Subclass Code 00 PCI Host Bridge Program Class Code 00 Not Used I O Base Register This register controls the mapping of the RavenMPIC control registers in PCI I O space Offset 08 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name CLASS REVID Operation R R Reset 060000 02 Offset 10 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 ...

Page 125: ... of the RavenMPIC control registers in PCI memory space IO MEM IO Space Indicator This bit is hard wired to a logic zero to indicate PCI memory space MTYPx Memory Type These bits are hard wired to zero to indicate that the RavenMPIC registers can be located anywhere in the 32 bit address space PRE Prefetch This bit is hard wired to zero to indicate that the RavenMPIC registers are not prefetchable...

Page 126: ... Address This field determines the start address of a particular memory area on the PCI bus which will be used to access MPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address END End Address This field determines the end address of a particular memory area on the PCI bus which will be used to access MPC bus resources The value of this field w...

Page 127: ...write posting is enabled for the corresponding PCI slave WEN Write Enable If set the corresponding PCI slave is enabled for write transactions REN Read Enable If set the corresponding PCI slave is enabled for read transactions PSOFFx PCI Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PCI address to determine the MPC address used for transfers from PCI...

Page 128: ...rom the MPC bus in Little Endian mode Offset CFB CFA CF9 CF8 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name CONFIG_ADDRESS EN BUS DEV FUN REG Operation R W R R W R W R W R W R R Reset 1 00 00 00 0 00 0 0 Offset CF8 CF9 CFA CFB Bit DH 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 ...

Page 129: ...ption of how this field is encoded Special Cycles This field must be written with all ones BUS Bus Number Configuration Cycles Identifies a targeted bus number If written with all zeros a Type 0 Configuration Cycle will be generated If written with any value other than all zeros then a Type 1 Configuration Cycle will be generated Special Cycles Identifies a targeted bus number If written with all ...

Page 130: ...spective from the MPC bus in Little Endian mode Offset CFF CFE CFD CFC Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name CONFIG_DATA Data D Data C Data B Data A Operation R W R W R W R W Reset n a n a n a n a Offset CFC CFD CFE CFF Bit DL 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 ...

Page 131: ...d interrupt delivery for external I O interrupts Direct Multicast interrupt delivery for Interprocessor and timer interrupts Four Interprocessor Interrupt sources Four timers Processor initialization control Architecture The Raven PCI Slave implements two address decoders for placing the RavenMPIC registers in PCI IO or PCI Memory space Access to these registers require MPC and PCI bus mastership ...

Page 132: ...rce is assigned a priority value in the range from 0 to 15 where 15 is the highest In order for delivery of an interrupt to take place the priority of the source must be greater than that of the destination processor Therefore setting a source priority to zero inhibits that interrupt Processor s Current Task Priority Each processor has a task priority register which is set by system software to in...

Page 133: ... targeted for the other processor or both processors There are four Interprocessor Interrupts IPI channels The interrupts are initiated by writing a bit in the IPI dispatch registers If subsequent IPIs are initiated before the first is acknowledged only one IPI will be generated The IPI channels deliver interrupts in the Direct Mode and can be directed to more than one processor 8259 Compatibility...

Page 134: ...mode of this error interrupt should be consistent Timers There is a divide by eight pre scaler which is synchronized to the Raven clock MPC processor clock The output of the prescaler enables the decrement of the four timers The timers may be used for system timing or to generate periodic interrupts Each timer has four registers which are used for configuration and control They are Current Count R...

Page 135: ... only one processor Therefore for externally sourced or I O interrupts multicast delivery is not supported The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority contained in the task register for that processor and when the priority of the interrupt is greater than any interrupt which is in service for that processor and when the priority of that...

Page 136: ...peration for the interrupt delivery logic If the preceding section is a satisfactory description of the interrupt delivery modes and the reader is not interested in the logic implementation this section can be skipped Figure 2 8 RavenMPIC Block Diagram 1917 9610 IPR Interrupt Selector_1 IRR_1 Interrupt Router ISR_1 interrupt signals Program Visible Registers Interrupt Selector_0 IRR_0 ISR_0 INT1 I...

Page 137: ...he internally generated interrupts use direct delivery mode with multicast capability there are two bits in the IPR one for each processor associated with each IPI and Timer interrupt source The MASK bits from the Vector Priority registers are used to qualify the output of the IPR Therefore if an interrupt condition is detected when the MASK bit is set that interrupt will be requested when the MAS...

Page 138: ... bits are used to store the source identification of each interrupt which is in service Therefore there is one bit for each possible interrupt priority and one bit for each possible interrupt source Interrupt Router The Interrupt Router monitors the outputs from the ISRs Current Task Priority Registers Destination Registers and the IRRs to determine when to assert a processor s INT pin When consid...

Page 139: ...his interrupt The priority from IRR_0 is greater than the highest priority in ISR_0 The priority from IRR_0 is greater than the contents of task register_0 Set2 The source ID in IRR_0 is from an external source The destination bit for processor 1 is a 1 for this interrupt The source ID in IRR_0 is not present is ISR_1 The priority from IRR_0 is greater than the highest priority in ISR_0 The priori...

Page 140: ...g table The Off field is the address offset from the base address of the RavenMPIC registers in the MPC IO or MPC Memory space Note that this map does not depict linear addressing The Raven PCI SLAVE has two decoders for generating the RavenMPIC select These decoders will generate a select and acknowledge all accesses which are in a reserved 256K byte range If the index into that 256KB block does ...

Page 141: ...OUNT REGISTER 01150 TIMER 1VECTOR PRIORITY REGISTER 01160 TIMER 1DESTINATION REGISTER 01170 TIMER 2 CURRENT COUNT REGISTER 01180 TIMER 2 BASE COUNT REGISTER 01190 TIMER 2 VECTOR PRIORITY REGISTER 011a0 TIMER 2 DESTINATION REGISTER 011b0 TIMER 3 CURRENT COUNT REGISTER 011c0 TIMER 3 BASE COUNT REGISTER 011d0 TIMER 3 VECTOR PRIORITY REGISTER 011e0 TIMER 3 DESTINATION REGISTER 011f0 INT SRC 0 VECTOR P...

Page 142: ...NT SRC 7 DESTINATION REGISTER 100f0 INT SRC 8 VECTOR PRIORITY REGISTER 10100 INT SRC 8 DESTINATION REGISTER 10110 INT SRC 9 VECTOR PRIORITY REGISTER 10120 INT SRC 9 DESTINATION REGISTER 10130 INT SRC 10 VECTOR PRIORITY REGISTER 10140 INT SRC 10 DESTINATION REGISTER 10150 INT SRC 11 VECTOR PRIORITY REGISTER 10160 INT SRC 11 DESTINATION REGISTER 10170 INT SRC 12 VECTOR PRIORITY REGISTER 10180 INT SR...

Page 143: ... 2 DISPATCH REGISTER PROC 0 20060 IPI 3 DISPATCH REGISTER PROC 0 20070 CURRENT TASK PRIORITY REGISTER PROC 0 20080 IACK REGISTER P0 200a0 EOI REGISTER P0 200b0 IPI 0 DISPATCH REGISTER PROC 1 21040 IPI 1 DISPATCH REGISTER PROC 1 21050 IPI 2 DISPATCH REGISTER PROC 1 21060 IPI 3 DISPATCH REGISTER PROC 1 21070 CURRENT TASK PRIORITY REGISTER PROC 1 21080 IACK REGISTER P1 210a0 EOI REGISTER P1 210b0 Tab...

Page 144: ...ber of the highest physical CPU supported There are two CPUs supported by this design CPU 0 and CPU 1 VID VERSION ID Version ID for this interrupt controller This value reports what level of the specification is supported by this implementation Version level of 02 is used for the initial release of the MPIC specification Offset 01000 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 ...

Page 145: ...rnal 8259 pair connected to the first interrupt source input pin 0 This bit will always be set to a one indicating mixed mode In the mixed mode 8259 interrupts are delivered using the priority and distribution mechanism of RavenMPIC The Vector Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources Offset 01020 Bit 3 ...

Page 146: ... P1 will assert the Soft Reset input of processor 1 Writing a 0 to it will negate the SRESET signal P0 PROCESSOR 0 Writing a 1 to P0 will assert the Soft Reset input of processor 0 Writing a 0 to it will negate the SRESET signal The Soft Reset input to the 604 is negative edge sensitive Offset 01080 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6...

Page 147: ...bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector Offset IPI 0 010A0 IPI 1...

Page 148: ...wing reset this register contains zero For the Raven implementation of MPIC on the MVME3600 or MVME4600 this register must be written with a value of 7de290 which is 66 8 MHz or 8 25 MHz which corresponds to a 66 MHz MPC bus Offset 010E0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation R R R R W Reset 00 00 00 FF ...

Page 149: ...Basecount Registers CI COUNT INHIBIT Setting this bit to one inhibits counting for this timer Setting this bit to zero allows counting to proceed Offset Timer 0 01100 Timer 1 01140 Timer 2 01180 Timer 3 011C0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name TIMER CURRENT COUNT T CC Operation R R Reset 0 00000000 Offset Timer 0 011...

Page 150: ...ted with this interrupt is set in the IPR the interrupt request will be generated ACT ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will ...

Page 151: ...d to processor 0 External Source Vector Priority Registers Offset Timer 0 01130 Timer 1 01170 Timer 2 011B0 Timer 3 011F0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name TIMER DESTINATION P1 P0 Operation R R R R R W R W Reset 00 00 00 00 0 0 Offset Int Src 0 10000 Int Src 2 Int Src15 10020 101E0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 ...

Page 152: ...bit to a zero enables active low or negative edge Setting this bit to a one enables active high or positive edge Only External Interrupt Source 0 uses this bit in this register SENSE SENSE This bit sets the sense for external interrupts Setting this bit to a zero enables edge sensitive interrupts Setting this bit to a one enables level sensitive interrupts For external interrupt sources 1 through ...

Page 153: ...rther interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated Offset Int Src 0 10010 Int Src 2 Int Src 15 10030 101F0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE DESTINATION P1 P0 Operation R R R R R W R W Res...

Page 154: ...owest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgement of the interrupt associated with this vector Raven Detected Errors Destination Register This register indicates the possible destinations for the Raven detected error interrupt source These interrupts operate ...

Page 155: ... processor Reading these registers returns zeros P1 PROCESSOR 1 The interrupt is directed to processor 1 P0 PROCESSOR 0 The interrupt is directed to processor 0 Interrupt Task Priority Registers Offset Processor 0 20040 20050 20060 20070 Processor 1 21040 21050 21060 21070 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name IPI DISPA...

Page 156: ...errupt Acknowledge is implemented as a read request to a memory mapped Interrupt Acknowledge register Reading the Interrupt Acknowledge register returns the interrupt vector corresponding to the highest priority pending interrupt Reading this register also has the following side effects The associated bit in the Interrupt Pending Register is cleared Reading this register will update the In Service...

Page 157: ...how an external interrupt is serviced 1 An external interrupt occurs 2 The processor state is saved in the machine status save restore registers A new value is loaded into the Machine State Register MSR The External Interrupt Enable bit in the new MSR MSRee is set to zero Control is transferred to the O S external interrupt handler 3 The external interrupt handler calculates the address of the Int...

Page 158: ...to recognize higher priority interrupt requests if any from the 8259 If none of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 a The device driver interrupt service routine associated with this interrupt vector is invoked b If the interrupt source was not the 8259 the interrupt handler issues an EOI request for this interrupt vector to th...

Page 159: ...PI dispatch registers Note that each IPI dispatch register is shared by both processors Each IPI dispatch register has two addresses but they are shared by both processors That is there is a total of four IPI dispatch registers in the RavenMPIC The IPI mechanism may be used for self interrupts by programming the dispatch register with the bit mask for the originating processor Dynamically Changing...

Page 160: ...ssor may read this register to retrieve the vector of the interrupt source which caused the interrupt 8259 Mode The 8259 mode bits control the use of an external 8259 pair for PC AT compatibility Following a reset this mode is set for pass through which essentially disables the advanced controller and passes an 8259 input on external interrupt source 0 directly through to processor zero During int...

Page 161: ...iority interrupts may continue to occur for an indeterminate number of cycles after the processor has updated the task priority register If this is not acceptable the interrupt controller architecture should recommend that if the task priority register is not implemented with the processor the task priority register should be updated only when the processor enter or exits an idle state Only when t...

Page 162: ......

Page 163: ... to provide the interface between the PowerPC 60x bus also called MPC60x bus or MPC bus and a 144 bit ECC DRAM memory system It also provides an interface to ROM Flash All Falcon bused signals are named using big endian bit ordering bit 0 is the most significant bit Summary of Features The following table summarizes the characteristics of the Falcon DRAM controller ASIC Function Features DRAM Inte...

Page 164: ...nal data paths Figure 3 3 shows the overall DRAM connections Error Notification for DRAM Software programmable Interrupt on Single Double Bit Error Error address and Syndrome Log Registers for Error Logging Does not provide TEA_ on Double Bit Error Chip has no TEA_ pin ROM Flash Interface Two blocks with each block being 16 bits wide 8 bits per Falcon or 64 bits wide 32 bits per Falcon Function Fe...

Page 165: ...owerPC Check Data FALCON FALCON Lower DRAM ARRAYS Check Data Upper DRAM ARRAYS Data 32Bits Lower DRAM Data 64 Bits Lower DRAM Address Control Lower DRAM Check bits 8 Bits Upper DRAM Data 64 Bits Upper DRAM Address Control Upper DRAM Check bits 8 Bits Upper PowerPC Data 32 Bits PowerPC Address Control Serial Bus PowerPC 60 x Bus ...

Page 166: ...r Chipset 3 Figure 3 2 Falcon Internal Data Paths Simplified 1901 9609 64 Bits PowerPC Side RD 0 63 HAMGEN DFF s HAMGEN DRAM Side LATCHES MUX D 0 31 64 Bits 64 Bits Latched D 64 Bits Corrected Data 8 Bits 8 Bits 8 Bits SYNDEC 64 Bits Uncorrected Data 64 Bits LATCHES CKD 0 7 ...

Page 167: ...ions DRAM BLOCK A UPPER DRAM BLOCK B UPPER DRAM BLOCK C UPPER DRAM BLOCK D UPPER BD_RAS_ CAS_ AC_RAS_ CAS_ RA OE_ WE_ RD0 63 CKD0 7 1902 9609 LOWER FALCON UPPER FALCON DRAM BLOCK A LOWER DRAM BLOCK B LOWER DRAM BLOCK C LOWER DRAM BLOCK D LOWER BD_RAS_ CAS_ AC_RAS_ CAS_ RA OE_ WE_ RD0 63 CKD0 7 ...

Page 168: ...he Falcon pair accesses the full 144 bit width of DRAM at once so that when the DRAM access time is reached not only is the first 64 bit double word of data ready to be transferred to the PowerPC 60x bus master but so is the next While the Falcon pair is presenting the first two double words to the PowerPC 60x bus it cycles CAS without cycling RAS to obtain the next two double words The Falcon pai...

Page 169: ...te cycle to the DRAM in order to complete When the Falcon pair can take advantage of address pipelining back to back single beat writes take 10 clocks to complete DRAM Speeds The Falcon pair can be configured for 3 different speeds of DRAM 50ns 60ns and 70ns When the Falcon pair is configured for 50ns DRAMs it assumes that the devices are Hyper Page parts When the Falcon pair is configured for 70n...

Page 170: ... Bus to DRAM Access Timing when Configured for 70ns Page Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 10 1 3 1 15 4 Beat Read after Idle Quad word misaligned 10 4 1 1 16 4 Beat Read after 4 Beat Read Quad word aligned 9 3 1 1 3 1 14 8 4 Beat Read after 4 Beat Read misaligned 7 2 1 4 1 1 13 8 4 Beat Write af...

Page 171: ... are averages and specific instances may be longer or shorter ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 9 1 2 1 13 4 Beat Read after Idle Quad word misaligned 9 3 1 1 14 4 Beat Read after 4 Beat Read Quad word aligned 7 3 1 1 2 1 11 7 4 Beat Read after 4 Beat Read misaligned 6 2 1 3 1 1 11 7 4 Beat Write after I...

Page 172: ...ers shown are averages and specific instances may be longer or shorter ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 8 1 1 1 11 4 Beat Read after Idle Quad word misaligned 8 2 1 1 12 4 Beat Read after 4 Beat Read Quad word aligned 5 2 1 1 1 1 8 5 4 Beat Read after 4 Beat Read misaligned 4 2 1 2 1 1 8 6 4 Beat Write ...

Page 173: ...owerPC 60x Bus to ROM Flash Access Timing when Configured for 64 bits 32 Bits per Falcon Table 3 5 PowerPC 60x Bus to ROM Flash Access Timing when Configured for 16 Bits 8 Bits per Falcon ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read 20 16 16 16 68 4 Beat Write N A N A N A N A N A 1 Beat Read 20 20 1 Beat Write 19 19 ACCESS TYPE CLOCK PERIODS R...

Page 174: ...on pair will have an associated data transfer the Falcon pair begins a read or write cycle to the accessed entity DRAM ROM Flash Internal Register as soon as the entity is free If the data transfer will be a read the Falcon pair begins providing data to the PowerPC 60x bus as soon as the entity has data ready and the PowerPC 60x data bus is granted If the data transfer will be a write the Falcon p...

Page 175: ...ves Each half is routed through a Falcon which multiplexes it with half of the DRAM data bus Each Falcon connects to 64 DRAM data bits and to 8 DRAM check bits The total DRAM array width is 144 bits 2 64 8 Cycle Types To support ECC the Falcon pair always deals with DRAM using full width 144 bit accesses When the PowerPC 60x bus master requests any size read of DRAM the Falcon pair reads 144 bits ...

Page 176: ...from DRAM merge with the write data and write the corrected merged data to DRAM Assert INT_ if so enabled N A 1 This cycle is not seen on the PowerPC 60x bus Write corrected data back to DRAM if so enabled Assert INT_ if so enabled Double Bit Error Terminate the PowerPC 60x bus cycle normally Provide miss corrected raw DRAM data to the PowerPC 60x bus master Assert INT_ if so enabled Assert MCP_ i...

Page 177: ...e DRAM tester is for in house manufacturing testing purposes only and should not be used by customers ROM Flash Interface The Falcon pair provides the interface for two blocks of ROM Flash Each block provides addressing and control for up to 64MB Note that no error checking ECC or Parity is provided for the ROM Flash The ROM Flash interface allows each block to be individually configured by jumper...

Page 178: ...r at reset time It also is available as a status bit and cannot be changed by software When the width status bit is cleared the block s ROM Flash is considered to be 16 bits wide where each Falcon interfaces to 8 bits In this mode the following rules are enforced a only single byte writes are allowed all other sizes are ignored and b all reads are allowed multiple accesses are performed to the ROM...

Page 179: ... ROM Flash Address Mapping when ROM Flash is 16 Bits Wide 8 Bits per Falcon PowerPC 60x A0 A31 ROM Flash A22 A0 ROM Flash Selected XX000000 000000 Upper XX000001 000001 Upper XX000002 000002 Upper XX000003 000003 Upper XX000004 000000 Lower XX000005 000001 Lower XX000006 000002 Lower XX000007 000003 Lower XX000008 000004 Upper XX000009 000005 Upper XX00000A 000006 Upper XX00000B 000007 Upper XX000...

Page 180: ...0 Upper X0000002 000000 Upper X0000003 000000 Upper X0000004 000000 Lower X0000005 000000 Lower X0000006 000000 Lower X0000007 000000 Lower X0000008 000001 Upper X0000009 000001 Upper X000000A 000001 Upper X000000B 000001 Upper X000000C 000001 Lower X000000D 000001 Lower X000000E 000001 Lower X000000F 000001 Lower X3FFFFF0 7FFFFE Upper X3FFFFF1 7FFFFE Upper X3FFFFF2 7FFFFE Upper Table 3 7 PowerPC ...

Page 181: ... CAS_ with OE_ then WE_ to one of the blocks during one of the four cycles This forms a read modify write which is a scrub cycle to that location After each of the 4 cycles the DRAM row address increments by one When it reaches all 1 s it rolls over and starts over at 0 Each time the row address rolls over the block that is scrubbed toggles between A and B X3FFFFF3 7FFFFE Upper X3FFFFF4 7FFFFE Low...

Page 182: ... one of the four cycles This forms a read modify write which is a scrub cycle to that location After the second and fourth cycles the DRAM row address increments by one When it reaches all 1 s it rolls over and starts over at 0 Each time the row address rolls over the block that is scrubbed toggles between A C and B D Every second time the row address rolls over which of the 4 cycles that is a scr...

Page 183: ... tester is in operation Chip Defaults Some jumper option kinds of parameters need to be configured by software in the Falcon pair These parameters include DRAM and ROM Flash attributes In order to set up these parameters correctly software needs some way of knowing about the devices that are being used with the Falcon pair One way of providing this information is by using the power up status regis...

Page 184: ... such that the actual update of the control register happens on the same CLOCK cycle in both chips Writes to the upper Falcon can be single byte or 4 byte Writes to the lower Falcon are ignored This duplicating of writes from upper to lower applies to the Falcon s internal registers and SRAM only No duplication is performed for writes to DRAM ROM Flash or the External Register set Programming Mode...

Page 185: ...n the upper half of the data bus goes to the upper Falcon and is automatically copied by hardware to the lower Falcon Internal register or test SRAM data written on the lower half of the data bus does not go to either Falcon in the pair but the access is terminated normally with TA_ See Figure 3 5 Upper FALCON 1903 9609 Upper Lower FALCON Data Bus Lower Data Bus CSR CSR MPC60x Master ...

Page 186: ...ke the internal register set there is no automatic copying of upper data to lower data for the external register set CSR read accesses can have a size of 1 2 4 or 8 bytes with any alignment CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned Some Tester registers are limited to 4 byte only accesses Figure 3 6 Figure 3 7 Figure 3 8 and Figure 3 9 show the memory map...

Page 187: ... Memory Map for Byte Reads to the CSR Upper Falcon Upper Falcon Upper Falcon Upper Falcon Lower Falcon Lower Falcon Lower Falcon Lower Falcon Upper Falcon Upper Falcon FEF80000 Lower Falcon FEF80001 FEF80002 FEF80003 FEF80004 FEF80005 FEF80006 FEF80007 FEF80008 FEF80009 FEF807FF ...

Page 188: ... 3 Figure 3 7 MemoryMapfor ByteWritesto theInternalRegister SetandTestSRAM 1906 9609 Both Falcons Both Falcons Both Falcons Both Falcons Both Falcons Both Falcons FEF80000 FEF80001 FEF80002 FEF80003 FEF80004 FEF80005 FEF80006 FEF80007 FEF80008 FEF80009 FEF807FF Writes not allowed Here ...

Page 189: ...Reads to the CSR Figure 3 9 MemoryMapfor4 ByteWritestotheInternalRegisterSetandTestSRAM Upper Falcon Lower Falcon Upper Falcon Lower Falcon FEF80000 Lower Falcon FEF80004 FEF80008 FEF8000C FEF807FC 1908 9609 Both Falcons Both Falcons FEF80000 FEF80004 FEF80008 FEF8000C FEF807FC Writes not allowed Here ...

Page 190: ...r Falcon To get the addresses for accesses to the lower Falcon add 4 to the address shown Since the only way to write to the lower Falcon s internal register set and test SRAM is to duplicate what is written to the upper Falcon only the addresses shown in the table should be used for writes to them Writes to the external register set are not duplicated from upper to lower so writes to them can be ...

Page 191: ...AM D BASE FEF80020 CLK FREQUENCY por FEF80028 refdis rwcb derc scien tien sien mien mcken FEF80030 elog escb esen embt esbt ERROR_SYNDROME esblk0 esblk1 scof SBE COUNT FEF80038 ERROR_ADDRESS FEF80040 scb0 scb1 swen rtest0 rtest1 rtest2 FEF80048 ROW ADDRESS COL ADDRESS FEF80050 ROM A BASE rom_a_64 ROM A SIZ rom_a_rv rom a en rom a we FEF80058 ROM B BASE rom_b_64 ROM B SIZ rom_b_rv rom b en rom b we...

Page 192: ...32 Bits FEF800C0 FEF800C8 TEST D2 Upper 8 Bits FEF800D0 TEST D2 Middle 32 Bits FEF800D8 TEST D2 Lower 32 Bits FEF800E0 FEF800E8 TEST D3 Upper 8 Bits FEF800F0 TEST D3 Middle 32 Bits FEF800F8 TEST D3 Lower 32 Bits FEF80100 CTR32 FEF80200 FEF803F8 FEF80400 PR_STAT1 FEF80408 FEF804F8 FEF80500 PR_STAT2 FEF80508 FEF807F8 FEF80800 FEF80BF8 TEST SRAM Table 3 9 Register Summary Continued ...

Page 193: ...it in the register set are as follows R The bit is a read only status bit R W The bit is readable and writable R C The bit is cleared by writing a one to itself C The bit is readable Writing a zero to the bit will clear it The possible states of the bits after local and power up reset are as defined below P The bit is affected by power up reset PURESET_ L The bit is affected by local reset HRESET_...

Page 194: ...number for the Falcon Revision ID General Control Register REVID The REVID bits are hard wired to indicate the revision level of the Falcon The value for the first revision is 01 for the second is 02 ADDRESS FEF80000 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME VENDID DEVID OPERATION READ ONLY READ ONLY RESET X X ADDRESS FEF80008 BIT 0 1 2 3 4 5 6 ...

Page 195: ...ffect of creating a hole in the DRAM memory map for accesses to ISA When isa_hole is cleared there is no hole created in the memory map adis When adis is clear fast page mode operation is used for back to back pipelined accesses to the same page within DRAM When it is set RAS is cycled between accesses This bit should normally be cleared unless the Falcon has a problem operating that way ram fref ...

Page 196: ...chip is connected to the lower half of the PowerPC 60x data bus and it does not drive TA_ or AACK_ When chipu is high this chip is connected to the upper half of the PowerPC 60x data bus and it drives TA_ and AACK_ chipu reflects the level that was on the ERCS_ pin during power up reset DRAM Attributes Register Warning To satisfy DRAM component requirements before the memory is used at start up so...

Page 197: ... 0 0 0 0 ram a siz0 ram a siz1 ram a siz2 ram b en 0 0 0 0 ram b siz0 ram b siz1 ram b siz2 ram c en 0 0 0 0 ram c siz0 ram c siz1 ram c siz2 ram d en 0 0 0 0 ram d siz0 ram d siz1 ram d siz2 OPERATION R W R R R R R W R W R W R W R R R R R W R W R W R W R R R R R W R W R W R W R R R R R W R W R W RESET 0 PL X X X X 0 P 0 P 0 P 0 PL X X X X 0 P 0 P 0 P 0 PL X X X X 0 P 0 P 0 P 0 PL X X X X 0 P 0 P ...

Page 198: ... 31 correspond to PowerPC 60x address bits 0 7 For larger DRAM sizes the lower significant bits of A B C D BASE are ignored This means that the block s base address will always appear at an even multiple of its size Note that bit 0 is MSB 100 128MB 18 8Mx8 s 64Mb 101 256MB 144 16Mx1 s 16Mb 36 16Mx4 s 64Mb 4 16Mx36 s 64Mb 16Mb SIMM DIMM 110 1024MB 144 64Mx1 s 64Mb 111 0MB Reserved ADDRESS FEF80018 ...

Page 199: ...mple 42 for 66 MHz When these bits are programmed this way the chip s prescale counter produces a 1 MHz output The output of the chip prescale counter is used by the refresher scrubber and the 32 bit counter After power up this register is initialized to 42 for 66MHz por por is set by the occurrence of power up reset It is cleared by writing a one to it Writing a 0 to it has no effect ADDRESS FEF8...

Page 200: ...k bit data rather than normal data The data path used for this mode is DH24 31 for check bit data controlled by the upper Falcon and DL24 31 for check bit data controlled by the lower Falcon Each 8 bit check bit location services 64 bits of normal data The 64 bits of data are all within the same Falcon Each Falcon provides every other 32 bits of data in the normal mode The figure below shows the r...

Page 201: ...st software gets a chance to check for the single bit error This can be avoided by disabling scrub writes Also note that writing bad check bits can set the elog bit in the Error Logger Register The writing of check bits causes the Falcon to perform a read modify write to DRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered ...

Page 202: ...writes by setting the swen bit if it was set before derc Setting derc to one alters Falcon pair operation as follows 1 During reads data is presented to the PowerPC 60x data bus uncorrected from the DRAM array 2 During single beat writes data is written without correcting single bit errors that may occur on the read portion of the read modify write Check bits are generated for the data being writt...

Page 203: ...l pin to pulse true mcken When mcken is set the detection of a multiple bit error during a PowerPC read or write causes the Falcon to pulse its machine check interrupt request pin MCP_ true When mcken is cleared the Falcon does not ever assert its MCP_ pin The Falcon never asserts its MCP_ pin in response to a multiple bit error detected during a scrub cycle Caution Note that the INT_ and MCP_ pin...

Page 204: ...per Falcon and from the lower Falcon When the upper Falcon logs an error it updates its attribute bits escb embt esbt ERROR_SYNDROME eblk0 eblk1 and ERROR_ADDRESS to match the results of the read cycle for its portion of the DRAM array When the lower Falcon logs an error it updates its attribute bits to match the results of the read cycle for its portion of the DRAM array While the logging of erro...

Page 205: ...us master was accessing DRAM Note that the DRAM Tester cannot cause an error to be logged esen When set esen allows errors that occur during scrubs to be logged When cleared esen does not allow errors that occur during scrubs to be logged embt embt is set by the logging of a multiple bit error in its Falcon It is cleared by the logging of a single bit error in its Falcon It is undefined after powe...

Page 206: ...BE COUNT rolls over from FF to 00 its Falcon sets the scof bit It also pulses the INT_ signal low if the scien bit is set Error_Address Register ERROR_ADDRESS These bits reflect the value that corresponds to bits 0 27 of the PowerPC 60x address bus when their Falcon last logged an error during a PowerPC access to DRAM They reflect the value of the DRAM row and column addresses if the error was log...

Page 207: ...st modes Table 3 12 shows their encodings Note that these test modes are not intended to be used once the chip is in a system ADDRESS FEF80040 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME scb0 scb1 0 0 0 0 0 swen 0 0 0 0 0 rtest0 rtest1 rtest2 OPERATION R R R R R R R R W R R R R R R W R W R W READ ZERO READ ZERO RESET 0 P 0 P X X X X X 0 P X X X X ...

Page 208: ...of ROW ADDRESS are used only when their DRAM devices are large enough to require them COL ADDRESS These bits form the column address counter used by the refresher scrubber for all blocks of DRAM The counter increments by one every eighth time the ROW ADDRESS rolls over COL ADDRESS is readable and writable for test purposes Note that within each block the most significant bits of COL ADDRESS are on...

Page 209: ...n of ROM_A_BASE and rom_a_siz should never be programmed such that ROM Flash Block A responds at the same address as the CSR DRAM External Register Set or any other slave on the PowerPC bus rom_a_64 rom_a_64 indicates the width of ROM Flash device devices being used for Block A When rom_a_64 is cleared Block A is 16 bits wide where each Falcon interfaces to 8 bits When rom_a_64 is set Block A is 6...

Page 210: ...s in the range FFF00000 FFFFFFFF as shown in the table below rom_a_rv is initialized at power up reset to match the value on the CKD0 pin Table 3 13 ROM Flash Block A Size Encoding rom a siz BLOCK SIZE 000 1MB 001 2MB 010 4MB 011 8MB 100 16MB 101 32MB 110 64MB 111 Reserved Table 3 14 rom_a_rv and rom_b_rv encoding rom_a_rv rom_b_rv Result 0 0 Neither Block is the source of reset vectors 0 1 Block ...

Page 211: ...e is attempted and rom a we is cleared the write does not happen but the cycle is terminated normally See Table 3 15 for details of ROM Flash accesses Table 3 15 Read Write to ROM Flash Cycle Transfer Size Alignment rom_x_64 rom_x_we Falcon Response write 1 byte X 0 0 Normal termination but no write to ROM Flash write 1 byte X 0 1 Normal termination write occurs to ROM Flash write 1 byte X 1 X No ...

Page 212: ...E and rom_b_siz should never be programmed such that ROM Flash Block B responds at the same address as the CSR DRAM External Register Set or any other slave on the PowerPC bus rom_b_64 rom_b_64 indicates the width of ROM Flash device devices being used for Block B When rom_b_64 is cleared Block B is 16 bits wide where each Falcon interfaces to 8 bits When rom_b_64 is set Block B is 64 bits wide wh...

Page 213: ...as shown in Table 3 14 on page 3 48 rom_b_rv is initialized at power up reset to match the inverse of the value on the CKD1 pin rom b en When rom b en is set accesses to Block B ROM Flash in the address range selected by ROM B BASE are enabled When rom b en is cleared they are disabled rom b we When rom b we is set writes to Block B ROM Flash are enabled When rom b we is cleared they are disabled ...

Page 214: ...ts once per microsecond if the CLK_FREQUENCY register has been programmed properly Notice that CTR32 is cleared by power up and local reset It does not exist in Revision 1 of Falcon Note When the system clock is a fractional frequency such as 66 67 MHz CTR32 will count at a fractional amount faster or slower than 1MHz depending on the programming of the CLK_FREQUENCY Register Test SRAM Deleted ADD...

Page 215: ...isters in Chapter 1 especially the System Configuration Register SYSCR and the Memory Configuration Register MEMCR Power Up Reset Status Register 2 PR_STAT2 PR_STAT2 power up reset status reflects the value that was on the RD32 RD63 signal pins at power up reset This register is read only ADDRESS FEF80400 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAM...

Page 216: ...t if the devices are less than 32 bits wide reads to unused data lanes will yield undefined data Note that writes are restricted to one or 4 byte length only 4 byte writes can be used for any size device data should be placed on the correct portion of the data bus so that valid data is written to the device Data duplication is turned off for the EXTERNAL REGISTER SET so writes can be to either the...

Page 217: ...the code will be split so that every other 4 byte segment goes in each device Writing to the Control Registers Software should not change control register bits that affect DRAM operation while DRAM is being accessed Because of pipelining software should always make sure that the two accesses before and after the updating of critical bits are not DRAM accesses A possible scenario for trouble would ...

Page 218: ...e in the DRAM Attributes Register offset FEF80010 The delay is intended to make sure that the bank has been refreshed at least eight times before it is used The 500µs is sufficient as the CLK Frequency Register on page 3 37 offset FEF80020 is within a factor of two of matching the actual 60x clock frequency The following routine can be used to size DRAM for the Falcon Initialize the Falcon control...

Page 219: ...ary depending on the size that is currently being checked and are specified in Table 3 17 on page 3 58 Table 3 18 on page 3 59 shows how PowerPC addresses correspond to DRAM row column addresses 5 Read back all of the addresses that have been written If all of the addresses still contain exactly what was written then the block s size has been found It is the size for which the block is currently p...

Page 220: ...ead The following table shows the addresses that go with each size Table 3 17 Sizing Addresses 1024MB 256MB 128MB 64MB 32MB 16MB 00000000 20000000 00000000 02000000 08000000 0A000000 00000000 00002000 02000000 02002000 04000000 04002000 06000000 06002000 00000000 00002000 02000000 02002000 00000000 00001000 00002000 00003000 01000000 01001000 01002000 01003000 00000000 ...

Page 221: ...e 3 62 for an explanation of this Table 3 18 PowerPC 60x Address to DRAM Address Mappings RA Block Size V 0 1 2 3 4 5 6 7 8 9 10 11 12 16MB ROW A19 A18 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 32MB ROW A18 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 64MB ROW A18 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A6 A18 ...

Page 222: ... ckd0 01 rd1 4C rd17 13 rd33 C4 rd49 31 ckd1 02 rd2 2C rd18 0B rd34 C2 rd50 B0 ckd2 04 rd3 2A rd19 8A rd35 A2 rd51 A8 ckd3 08 rd4 E9 rd20 7A rd36 9E rd52 A7 ckd4 10 rd5 1C rd21 07 rd37 C1 rd53 70 ckd5 20 rd6 1A rd22 86 rd38 A1 rd54 68 ckd6 40 rd7 19 rd23 46 rd39 91 rd55 64 ckd7 80 rd8 25 rd24 49 rd40 52 rd56 94 rd9 26 rd25 89 rd41 62 rd57 98 rd10 16 rd26 85 rd42 61 rd58 58 rd11 15 rd27 45 rd43 51 ...

Page 223: ... A8 rd51 C8 rd47 E8 09 29 rd48 49 rd24 69 89 rd25 A9 C9 E9 rd4 0A 2A rd3 4A rd0 6A 8A rd19 AA CA EA 0B rd18 2B 4B 6B 8B AB CB EB 0C 2C rd2 4C rd1 6C 8C rd15 AC CC EC 0D rd14 2D 4D 6D 8D AD CD ED 0E rd13 2E 4E 6E 8E AE CE EE 0F 2F 4F rd44 6F 8F AF CF EF 10 ckd4 30 50 70 rd53 90 B0 rd50 D0 rd46 F0 11 31 rd49 51 rd43 71 91 rd39 B1 D1 F1 12 32 rd63 52 rd40 72 92 rd16 B2 D2 F2 13 rd17 33 53 73 93 B3 D3...

Page 224: ... Memory Controller Chipset 3 Data Paths Because of the Falcon pair architecture data paths can be confusing Figure 3 10 attempts to show the placement of data that is written by a PowerPC master to DRAM Table 3 21 shows the same information in tabular format ...

Page 225: ...ure 3 63 3 Figure 3 10 PowerPC Data to DRAM Data Correspondence 1909 9609 Lower Falcon s DRAM Upper Falcon s DRAM ra12 1 PowerPC Data ra12 0 ra12 1 ra12 0 rd63 dl31 rd32 rd31 rd0 rd63 rd32 rd31 rd0 dl0 dh31 dh0 a 27 28 0 a 27 28 1 a 27 28 2 a 27 28 3 ...

Page 226: ... 0 0 dl 24 31 0 rd 24 31 0 1 dh 00 07 0 rd 32 39 0 1 dh 08 15 0 rd 40 47 0 1 dh 16 23 0 rd 48 55 0 1 dh 24 31 0 rd 56 63 0 1 dl 00 07 0 rd 32 39 0 1 dl 08 15 0 rd 40 47 0 1 dl 16 23 0 rd 48 55 0 1 dl 24 31 0 rd 56 63 1 0 dh 00 07 1 rd 00 07 1 0 dh 08 15 1 rd 08 15 1 0 dh 16 23 1 rd 16 23 1 0 dh 24 31 1 rd 24 31 1 0 dl 00 07 1 rd 00 07 1 0 dl 08 15 1 rd 08 15 1 0 dl 16 23 1 rd 16 23 1 0 dl 24 31 1 ...

Page 227: ...ola the Universe is compliant with the VME64 specification and is tuned to the new generation of high speed processors The Universe is ideally suited for CPU boards acting as both master and slave in the VMEbus system and is particularly fitted for PCI local systems The Universe is manufactured in a CMOS process Product Overview Features Fully compliant 64 bit 33 MHz PCI local bus interface Fully ...

Page 228: ...ption Architectural Overview This section introduces the general architecture of the Universe This description makes reference to the functional block diagram provided in Figure 4 1 that follows Notice that for each of the interfaces VMEbus and PCI bus there are three functionally distinct modules master module slave module and interrupt module These modules are connected to the different function...

Page 229: ...nels illustrated below Figure 4 1 Architectural Diagram for the Universe VME Slave VME Master VME Interrupts posted writes FIFO coupled read logic DMA bidirectional FIFO Interrupt Handler Interrupter Register Channel VMEbus Slave Channel posted writes FIFO prefetch read FIFO coupled read PCI Bus Slave Channel Interrupt Channel PCI Master PCI Slave PCI Interrupts VMEbus PCI BUS PCI Bus Interface VM...

Page 230: ...he PCI bus This means that the VMEbus is unavailable to other masters while the PCI bus transaction is executed Read transactions may be prefetched or coupled If enabled by the user a prefetched read is initiated when a VMEbus master requests a block read transaction BLT or MBLT and this mode is enabled When the Universe receives the block read request it begins to fill its Read Data FIFO RDFIFO u...

Page 231: ...O and the PCI bus master receives data acknowledgment from the Universe with zero wait states Meanwhile the Universe obtains the VMEbus and writes the data to the VMEbus resource independent of the initiating PCI master Refer to Posted Writes in the Universe User Manual for a full description of this operation To allow PCI masters to perform RMW and ADOH cycles the Universe provides a Special Cycl...

Page 232: ...t sources must be routed to a single INT pin For VMEbus interrupt outputs the Universe interrupter supplies an 8 bit STATUS ID to a VMEbus interrupt handler during the IACK cycle and optionally generates an internal interrupt to signal that the interrupt vector has been provided Refer to VMEbus Interrupt Generation in the Universe User Manual Interrupts mapped to PCI bus outputs are serviced by th...

Page 233: ...AFIFO Following specific rules of DMAFIFO operation refer to FIFO Operation and Bus Ownership in the Universe User Manual it then acquires the destination bus and writes data from its DMAFIFO The DMA controller can be programmed to perform multiple blocks of transfers using entries in a linked list The DMA will work through the transfers in the linked list following pointers at the end of each lin...

Page 234: ...isms Figure 4 2 UCSR Access Mechanisms Universe Register Map Table 4 1 below lists the Universe registers by address offset Tables in the Universe User Manual provide detailed descriptions of each register VMEbus Configuration and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS UDSR PCI CONFIGURATION SPACE PCICS 4 Kbytes 1895 9609 ...

Page 235: ...ister PCI_CSR 008 PCI Configuration Class Register PCI_CLASS 00C PCI Configuration Miscellaneous 0 Register PCI_MISC0 010 PCI Configuration Base Address Register PCI_BS 014 PCI Unimplemented 018 PCI Unimplemented 01C PCI Unimplemented 020 PCI Unimplemented 024 PCI Unimplemented 028 PCI Reserved 02C PCI Reserved 030 PCI Unimplemented 034 PCI Reserved 038 PCI Reserved 03C PCI Configuration Miscellan...

Page 236: ..._BD 148 PCI Slave Image 3 Translation Offset LSI3_TO 14C 16C Universe Reserved 170 Special Cycle Control Register SCYC_CTL 174 Special Cycle PCI bus Address Register SCYC_ADDR 178 Special Cycle Swap Compare Enable Register SCYC_EN 17C Special Cycle Compare Data Register SCYC_CMP 180 Special Cycle Swap Data Register SCYC_SWP 184 PCI Miscellaneous Register LMISC 188 Special PCI Slave Image SLSI 18C ...

Page 237: ...Status VINT_STAT 318 VMEbus Interrupt Map 0 VINT_MAP0 31C VMEbus Interrupt Map 1 VINT_MAP1 320 Interrupt Status ID Out STATID 324 VIRQ1 STATUS ID V1_STATID 328 VIRQ2 STATUS ID V2_STATID 32C VIRQ3 STATUS ID V3_STATID 330 VIRQ4 STATUS ID V4_STATID 334 VIRQ5 STATUS ID V5_STATID 338 VIRQ6 STATUS ID V6_STATID 33C VIRQ7 STATUS ID V7_STATID 340 3FC Universe Reserved 400 Master Control MAST_CTL 404 Miscel...

Page 238: ...ve Image 2 Bound Address Register VSI2_BD F34 VMEbus Slave Image 2 Translation Offset VSI2_TO F38 Universe Reserved F3C VMEbus Slave Image 3 Control VSI3_CTL F40 VMEbus Slave Image 3 Base Address Register VSI3_BS F44 VMEbus Slave Image 3 Bound Address Register VSI3_BD F48 VMEbus Slave Image 3 Translation Offset VSI3_TO F4C F6C Universe Reserved F70 VMEbus Register Access Image Control Register VRA...

Page 239: ...re are problems with the Universe chip after a PCI reset Problem Description The Universe chip is being enabled on the PCI bus after a PCI reset The problem does not occur after a board reset or power up The Universe is causing the bye command to hang the system The Universe Master Enable and Memory Enable in the PCI_CSR Configuration Space register are enabled even before the PCI_BS register has ...

Page 240: ...hod 1 1 Modify the PCI probe code to disable each PCI device prior to writing its configuration space BS registers This will prevent the Universe from being active on the PCI bus while it has a base addr of 0 2 Once the Universe has been assigned a valid PCI Base Address enable register space access and disable the LSI0 slave image by clearing the EN bit of the LSI0_CTL register Method 2 The port ...

Page 241: ...their own Many of these customers replace Motorola s firmware or overwrite the firmware settings for the Universe chip These customers may run into this problem Customers should not encounter any problems if they leave Motorola s PPCBug debugger intact Examples Example 1 MVME2600 Series Board Exhibits Problem Use an MVME2600 series board to exhibit the problem Conditions MVME260x running PPCOF2 0 ...

Page 242: ...Manually enable access to the Universe register set and read the LSI0 registers CTL BS BD TO 80820000 0 20000000 0 This means that the PCI reset changed the image as follows from supervisor address modifier to user from PCI space base address 1012000 to 0 size of 2000 0000 constant from VME address range 4000 0000 thru 5fff ffff to a new VMEbus range of 0 thru 1fff ffff It is still enabled ...

Page 243: ...I probing PCI probe list d c e f 10 1 After a P U reset before the init code has written the registers the LSI0 register settings are CTL BS BD TO 800000 0 0 0 2 Run the init code and the LSI0 registers become CTL BS BD TO 80821000 3000000 300a000 4d000000 3 After a bye before the init code has run CTL BS BD TO 80820000 0 0 0 Therefore the PCI reset caused the following changes in the LSI0 image f...

Page 244: ...t code ran the LSI0 values are 800000 0 0 0 5 Do NOT run the init code but press push button RESET and the values become 830001 f0000000 f0000000 0 6 Run the vme3 init code and the values are set to accommodate env parameters 80821000 3000000 23000000 3d000000 7 Do a bye The values before the init code runs are 80820000 0 20000000 0 This gets the same results with the MVME360x as with the MVME260x...

Page 245: ...e Motorola engineers had seen for example that the LSI0_BS LSI0_BD and LSI0_TO values change as well as the LSI0_CTL fields for program super and vct He checked to see if this is in fact what the Universe is supposed to do The following are his results Register Before RST After RST LSI0_CTL 8082_5FFF 8082_0001 LSI0_BS FFFF_FFFF F000_0000 LSI0_BD FFFF_FFFF F000_0000 LSIO_TO FFFF_FFFF 0000_0000 Expl...

Page 246: ......

Page 247: ...nts on the MVME3600 series and MVME4600 series are as follows Upon power up the PIB defaults to a round robin arbitration mode The relative priority of each request grant pair can be customized via the PCI Priority Control Register 1 Refer to the W83C553 Data Book for additional details Table 5 1 PCI Arbitration Assignments PCI BUS REQUEST PCI Master s PIB internal PIB CPU Secondary Ethernet Secon...

Page 248: ...The interrupt architecture of the MVME3600 4600 series VME Processor Modules is shown in the following figure Figure 5 1 MVME3600 4600 Series Interrupt Architecture 11559 00 9609 PIB 8259 Pair Processor INT_ MCP_ Processor INT_ MCP_ RavenMPIC INT SERR_ PERR_ PCI Interrupts ISA Interrupts ...

Page 249: ...troller Chip for details on the RavenMPIC The following table shows the interrupt assignments for the RavenMPIC on the MVME3600 4600 series Table 5 2 RavenMPIC Interrupt Assignments MPIC IRQ Edge Level Polarity Interrupt Source Notes IRQ0 Level High PIB 8259 1 IRQ1 Edge Low Falcon ECC Error 2 IRQ2 Level Low PCI Ethernet 4 IRQ3 Level Low PCI SCSI 4 IRQ4 Level Low PCI Graphics 4 IRQ5 Level Low PCI V...

Page 250: ...tionally equivalent to two 82C59 interrupt controllers Except for IRQ0 IRQ1 IRQ2 IRQ8_ and IRQ13 each of the interrupt lines can be configured for either edge sensitive mode or level sensitive mode by programming the appropriate ELCR registers in the PIB There is also support for four PCI interrupts PIRQ3_ PIRQ0_ The PIB has four PIRQ Route Control Registers to allow each of the PCI interrupt line...

Page 251: ...wing figure shows the interrupt structure of the PIB Figure 5 2 PIB Interrupt Handler Block Diagram 1897 9609 IRQx PIRQ Route Control Register PIRQ Route Control Register PIRQ Route Control Register PIRQ Route Control Register PIRQ3_ IRQx PIRQ2_ IRQx PIRQ1_ IRQx PIRQ0_ Controller 2 INT2 IRQ8 IRQ9 IRQ11 IRQ10 IRQ12 IRQ13 IRQ14 IRQ15 0 1 2 3 4 5 6 7 Controller 1 INT1 Timer1 Counter0 IRQ1 IRQ3 IRQ4 I...

Page 252: ...3 IRQ8_ INT2 Edge Low ABORT Switch Interrupt 4 IRQ9 Level High Z8536 CIO 3 4 Z85230 ESCC 5 IRQ10 PIRQ0_ Level Low PCI Ethernet Interrupt 3 5 6 6 IRQ11 PIRQ1_ Level Low Universe Interrupt LINT0 3 5 6 7 IRQ12 Edge High Mouse 8 IRQ13 Edge High Not Used 6 9 IRQ14 PIRQ2_ Level Low PCI SCSI Interrupt 3 5 6 10 IRQ15 PIRQ3_ Level Low PCI Graphics Interrupt 3 5 6 PMC Interrupt 3 5 6 7 11 IRQ3 INT1 Edge Hig...

Page 253: ...igher priority than the Z85230 ESCC This IRQ MUST be programmed for level sensitive mode 5 These PCI interrupts are routed to the ISA interrupts by programming the PRIQ Route Control Registers in the PIB The PCI to ISA interrupt assignments in this table are suggested Each ISA IRQ to which a PCI interrupt is routed to MUST be programmed for level sensitive mode Use this routing for PCI interrupts ...

Page 254: ...5 I O Reset via the Clock Divisor Register in the PIB 6 VMEbus SYSRESET signal 7 Local software reset via the Universe ASIC MISC_CTL Register 8 VME System Reset Via the Universe ASIC MISC_CTL Register The following table shows which devices are affected by various reset sources Table 5 4 Reset Sources and Devices Affected Device Affected Processor s Raven ASIC Falcon Chipset PCI Devices ISA Device...

Page 255: ...ain conditions there can be problems with the Universe chip after a PCI reset Refer to Chapter 4 Universe VMEbus to PCI Chip for the details VME System Software Reset MISC_CTL Register VME Local Software Reset MISC_CTL Register Hot Reset Port 92 Register PCI ISA Reset Clock Divisor Register Table 5 4 Reset Sources and Devices Affected Continued Device Affected Processor s Raven ASIC Falcon Chipset...

Page 256: ...ine Check Interrupt to the Processor s if so enabled MPC Bus Time Out Store Discard write data and terminate bus cycle normally Load Present undefined data to the MPC master Generate interrupt via RavenMPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Target Abort Store Discard write data and terminate bus cycle normally Load Return all 1 s and terminate bus ...

Page 257: ...oftware for example NT and big endian software for example AIX Because the PowerPC processor is inherently big endian PCI is inherently little endian and the VMEbus is big endian things do get rather confusing Figure 5 3 and Figure 5 4 show how the MVME3600 4600 series handles the endian issue in big endian and little endian modes ...

Page 258: ...ter Web Site Programming Details 5 Figure 5 3 Big Endian Mode Big Endian PROGRAM 1898 9609 Raven Universe Falcons DRAM Big Endian Little Endian Big Endian Little Endian PCI Local Bus VMEbus N way Byte Swap N way Byte Swap 60X System Bus ...

Page 259: ... 13 5 Figure 5 4 Little Endian Mode EA Modification XOR 1899 9609 Raven Universe Falcons DRAM Big Endian Little Endian Big Endian Little Endian PCI Local Bus VMEbus N way Byte Swap EA Modification 60X System Bus Big Endian Little Endian Little Endian PROGRAM ...

Page 260: ...ed to operate in big endian mode with the processor and the memory subsystem In little endian mode it reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done PCI Domain The PCI bus is inherently little endian and all devices connected directly to PCI will operate in little endian mode regardless of th...

Page 261: ...ME4600 series boards but no graphics on the MVME2600 series boards Universe s Involvement Since PCI is little endian and the VMEbus is big endian the Universe performs byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the mode of operation in the processor s domain VMEbus Domain The VMEbus is inherently big endian and all device...

Page 262: ...ond method the hardware must direct the Falcon chipset to map the FFF00000 FFFFFFFF address range to Bank B following a hard reset Bank A then can be programmed by code from Bank B Software can determine the mapping of the FFF00000 FFFFFFFF address range by examining the rom_b_rv bit in the Falcon s Rom B Base Size Register Table 5 6 ROM Flash Bank Default rom_b_rv Default Mapping for FFF00000 FFF...

Page 263: ...om computer literature To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature Table A 1 Motorola Computer Group Documents Document Title Publication Number MVME3600 4600 Series VME Processor Modules Installation and Use V36V46A IH PPCBug Firmware Package User s Manual Parts 1 and 2 PPCBUGA1 UM PPCBUGA2 UM PPCBug Diagnostics Manual PP...

Page 264: ...150 Web Site http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR IBM Microelectronics PowerPC604e User Manual Web Site http www chips ibm com techlib products powerpc manuals MPC604EUM AD G522 0330 00 PowerPCTM Microprocessor Family The Programming Environment for 32 Bit Microprocessors Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 ...

Page 265: ...Microelectronics Web Site http eu st com stonline index shtml M48T59 SYM 53CXX was NCR 53C8XX Family PCI SCSI I O Processor Data Manual LSI Logic Corporation Web Site http www lsilogic com SYM53C875 875E Data Manual SCC Serial Communications Controller User s Manual for Z85230 and other Zilog parts Web Site http www zilog com pdfs serial scc_escc_iscc_manual contents html SCC ESCC User s Manual Z8...

Page 266: ...er System Interface 2 SCSI 2 Draft Document Global Engineering Documents Web Site http global ihs com index cfm X3 131 1990 VME64 Specification VITA VMEbus International Trade Association Web Site http www vita com ANSI VITA 1 1994 IEEE Common Mezzanine Card Specification CMC Institute of Electrical and Electronics Engineers Inc Web Site http standards ieee org catalog P1386 Draft 2 0 IEEE PCI Mez...

Page 267: ... Corporation Web Site http www ibm com MPR PPC RPU 02 PowerPC Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 Web Site http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com OR Morgan Kaufmann Publishers Inc Telephone 415 392 2665 T...

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Page 269: ...gram description 2 64 block diagrams 3 2 block_A B C D configurations 3 35 blocks A and or B present blocks C and D not present 3 19 blocks A and or B present blocks C and or D present 3 20 bus interface 60x 3 12 C cache coherency 3 12 cache coherency restrictions 3 13 chip defaults 3 21 CHRP memory map example 1 10 CLK FREQUENCY 3 37 CLK Frequency Register 3 37 clock frequency 3 37 Column Address...

Page 270: ... 42 error logging 3 15 error notification and handling 5 10 error reporting 3 14 ERROR_ADDRESS 3 44 ERROR_SYNDROME 3 43 esbt 3 43 escb 3 43 esen 3 43 example 1 4 15 example 2 4 17 example 3 4 19 examples 4 15 exceptions 5 8 external interrupt service 2 85 External Register Set 3 54 external register set 3 21 external register set reads and writes 3 22 External Source Destination Registers 2 81 Ext...

Page 271: ... Reg ister 1 40 Location Monitor Upper Base Address Reg ister 1 40 M manufacturers documents A 2 mcken 3 41 Memory Base Register 2 53 Memory Configuration Register MEMCR 1 27 memory map for 4 byte reads to the CSR 3 27 memory map for 4 byte writes to the internal register set and test SRAM 3 27 memory map for byte reads to the CSR 3 25 memory map for byte writes to the internal register set and te...

Page 272: ... Registers 2 55 PCI slave response command types 2 15 PCI spread I O address translation 2 22 PCI to MPC address decoding 2 12 PCI to MPC address translation 2 13 PCI write posting 2 17 PCI Ethernet 5 15 PCI graphics 5 15 PCI SCSI 5 14 performance 3 6 PIB DMA channel assignments 1 47 PIB interrupt handler block diagram 5 5 PIB PCI ISA interrupt assignments 5 6 PowerPC 60x to ROM Flash Address Map ...

Page 273: ...bit 3 38 reads writes to ROM Flash 3 49 refdis 3 38 Refresh Counter Test control bits 3 45 Refresh Scrub 3 19 Refresh Scrub Address Register 3 46 register bit descriptions 3 31 register summary 3 28 registers Universe Control and Status Reg isters UCSR 4 7 related documentation A 1 related specifications A 4 reset sources and devices affected 5 8 reset state 2 86 revision ID bits 3 32 Revision ID ...

Page 274: ...79 Timer Frequency Register 2 76 Timer Vector Priority Registers 2 78 timers 2 62 timing DRAM access 3 8 3 9 3 10 timing ROM Flash access 3 11 transaction ordering 2 29 trun bit 3 52 tsse bit 3 52 U UCSR access mechanisms 4 8 Universe VMEbus to PCI chip 4 1 Universe as PCI master 4 5 Universe as PCI slave 4 5 Universe as VMEbus master 4 4 Universe as VMEbus slave 4 4 Universe chip problems after a...

Page 275: ...re big endian 2 25 when MPC devices are little endian 2 26 writing to the control registers 3 55 Z Z85230 ESCC and Z8536 CIO registers and port pins 1 43 Z8536 CIO port pins 1 44 Z8536 CIO port pins assignment 1 44 Z8536 Z85230 access registers 1 43 Z8536 Z85230 registers 1 43 ...

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