Motorola MC92603, Reference Manual

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7-6
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
MOTOROLA
AC Electrical Characteristics
7.3.2 Receiver Interface Timing
The data output timing at the receiver interface may be single data rate (non-DDR) or
double data rate (DDR) as described in Section 3.4, “Receiver Interface Configuration.”
Additionally, the valid data is sourced simultaneously with, or centered on, the
RECV_x_CLK output, depending on the state of the control signal, RECV_CLK_CENT.
When the control signal RECV_CLK_CENT = high, the data is centered about the receiver
clock edge. When RECV_CLK_CENT = low, the receiver clock edge is aligned
(co-incident) with the data. See Section 3.6, “Receiver Interface Timing Modes,” for more
on receiver interface timing.
Table 7-6 shows the receiver clock cycle time and the target or typical offset of the clock
edge with respect to the data depending on the device application configuration. Note that
the complement of the receiver clock, RECV_x_RCLK_B, is only valid and available in
TBI and RTBI Ethernet compliant applications modes.
Table 7-6 also lists references to timing figures in the following receiver interface timing
sections.
Table 7-6. Target Receiver Clock Offset Relative to Data
Application
Mode
DDR
TBIE and
COMPAT =
High
HSE
Receiver
Clock Cycle
Time
1
(ns)
1
Assumes 125-MHz reference clock if HSE is disabled and 62.5-MHz reference clock if HSE is enabled.
RECV_x_
RCLK
RECV_x_
RCLK_B
Clock Offset
to Data
(ns)
Reference
Figure No.
GMII or 8-/10-bit
backplane Low False Low 8 Valid Low 4 7-3
Low False High 16 Valid Low 8 7-3
Ethernet TBI Low True Low 16 Valid Valid 4 7-4
Low True High 32 Valid Valid 8 7-4
RGMII or 4-/5-bit
backplane High False Low 8 Valid Low 2 7-5
High False High 16 Valid Low 4 7-5
Ethernet RTBI High True Low 8 Valid Valid 2 7-6
High True High 16 Valid Valid 4 7-6