Motorola MC92603, Reference Manual

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MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
MOTOROLA
Receiver Interface Timing Modes
If WSE is high, then all enabled receivers (those that have XCVR_x_DISABLE negated
low) will be aligned into a 16-, 24-, or 32-bit word (depending on the states of the various
XCVR_x_DISABLE signals). If the receiver on channel A is disabled, then do not select
the clock from channel A as the recovered clock for all the channels.
3.6 Receiver Interface Timing Modes
The receiver interface is timed to the recovered clock (link partner’s clock) or to the
reference clock (local clock), depending on the state of the recovered clock enable, RCCE,
signal. RCCE enables timing relative to the recovered clock when asserted and enables
timing relative to the reference clock when negated.
The receiver interface clock signals, RECV_x_RCLK, will always be present when the
PLL is in lock. This is true even if there is no signal present on the serial inputs or if the
receiver has not achieved alignment or byte sync. The frequency of the receiver clock will
be the local reference clock until synchronization is achieved. The RECV_x_RCLK clock
signals, however, are not present during power up or when the MC92603 is in reset mode
and the PLL is not locked.
All receiver channels data outputs are source synchronous with their respective
RECV_x_RCLK outputs. They may be configured to be source aligned or source centered
with their respective RECV_x_RCLK outputs. The configuration signal,
RECV_CLK_CENT, when asserted high, will center the receiver clocks relative to the data
and status outputs.
NOTE
The receiver clock complement, RECV_x_RCLK_B, is only
provided in the TBIE/RTBI Ethernet compliant application
modes (TBIE and COMPAT = high). If either TBIE or
COMPAT is low, then RECV_x_RCLK_B is always low.
3.6.1 Recovered Clock Timing Mode (RCCE = High)
With RCCE asserted, the receiver clock signal, RECV_x_RCLK, is generated by the
receiver and, on average, runs at the reference clock frequency of the transmitter (link
partner’s clock) at the other end of the link. The recovered clock is not generated by a clock
recovery PLL but by monitoring the receive FIFO.
When RCCE is high, the configuration signal, RECV_REF_A, is used to select the clock
to be used. If RECV_REF_A is high, channel A’s recovered clock is used for all four
channels. If it is low, then each channel uses its own recovered clock. If RECV_REF_A is
high, it is assumed that all four channels are operating at an identical frequency.
In order to track a transmitter frequency that is offset from the receiver’s reference clock
frequency, the duty cycle and period of the RECV_x_RCLK is modulated. For example, if