Motorola MC92603, Reference Manual

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7-10
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual
MOTOROLA
AC Electrical Characteristics
7.3.2.2.2 Receiver, DDR Centered Clock Timing (Ethernet RTBI Mode)
Figure 7-6 provides the receiver interface, DDR timing diagram when TBIE is asserted
high and COMPAT is asserted high.
Table 7-8 provides the receiver, DDR timing specifications when TBIE is asserted high and
COMPAT is asserted high.
Figure 7-6. Receiver, DDR Timing Diagram
(TBIE = High and COMPAT = High)
Table 7-10. Receiver, DDR Timing Specification
(TBIE = High and COMPAT = High)
Symbol Characteristic
1
1
10 pF output load.
Aligned Clock Centered Clock
Unit Note
Min Max Min Max
T
1
Output valid time before rising edge of
RECV_x_RCLK or RECV_x_RCLK_B –0.500 0.500 1.440 — ns
2
2
Full-speed, HSE = low.
–1.000 1.000 3.440 — ns
3
3
Half-speed, HSE = high.
T
2
Output valid time after rising edge of
RECV_x_RCLK or RECV_x_RCLK_B 3.000 — 1.420 — ns
2
7.000 — 3.420 — ns
3
T
3
RECV_x_RCLK or RECV_x_RCLK_B cycle
time 15.800 16.200 15.800 — ns
2
31.800 32.200 31.800 — ns
3
T
4
Rising edge of RECV_x_RCLK to rising
edge of RECV_x_RCLK_B 7.800 8.200 7.800 8.200 ns
2
15.800 16.200 15.800 16.200 ns
3
T
5
Falling edge of either clock to rising edge of
other clock –0.200 0.200 –0.200 0.200 ns
2
–0.200 0.200 –0.200 0.200 ns
3
T
1
T
2
RECV
_x_
3
–
0
RECV
_x_
DV
RECV
_x_
RCLK
T
1
T
2
RECV
_x_
RCLK_B
RECV
_x_
COMMA
T
4
T
3
T
5