Motorola MC92603, Reference Manual

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MOTOROLA Chapter 2. Transmitter 2-5
Transmitter Interface Configuration
Transmit data is sampled and stored in the input FIFO on the rising edge (single data rate)
of the appropriate transmit clock, if DDR is low, or both edges (double data rate) of the
transmit clock if DDR is high. The FIFO accepts data to be transmitted and synchronizes it
to the internal clock domain.
The 8B/10B encoder takes an 8-bit data/control from the input register and encodes it into
10-bit transmission characters. The fibre channel 8B/10B coding standard is followed [1,2].
A detailed explanation of the 8B/10B coding scheme is offered in Appendix B, “8B/10B
Coding Scheme.” Running disparity is maintained, and the appropriate transmission
characters are produced, maintaining DC balance and sufficient transition density to allow
reliable data recovery at the receiver. The 8B/10B encoder is bypassed if TBIE is asserted
high.
The transmitter data interface operates at high frequency (nominally 125 MHz). In order to
ease development of devices that interface with the Gigabit Ethernet transceiver, all
transmitter data input interfaces are source-synchronous. The data for each channel has its
own dedicated clock input. This allows the clock at the source of the data to be routed with
the data ensuring matched delay and timing. However, if per-channel clock sources are not
available or deemed unnecessary, all channels may be clocked by a common clock source.
This is enabled by asserting XMIT_REF_A high. When XMIT_REF_A is high, the
XMIT_A_CLK becomes the interface clock for all active channels.
The configuration settings of the MC92603 affect the legal range of clock frequencies at
which it may be operated. Table 5-1 shows legal transmit interface clock frequencies for all
modes of operation. All transmit interface clock inputs, XMIT_x_CLK, and the PLL
reference clock inputs, REF_CLK, must have identical frequencies. The transmit data
interface tolerates
±
180
°
of transmit interface clock phase drift relative to the PLL
reference clock input.
2.3.1 Transmit Driver Operation
The transmit driver outputs the transmission characters serially across the link. Two bits per
internal transceiver clock, rx_clock, one each on the rising and falling clock edges, are
transmitted differentially from the XLINK_x_P/XLINK_x_N outputs. The internal
rx_clock runs at 625 MHz for 1-Gbps (1.25-Gbaud) operation and 312.5 MHz for
500-Mbps (625-Mbaud) operation.
The transmitter driver (high-speed serial link outputs) is a controlled impedance driver. The
impedance of the driver is programmable to 50 or 75
Ω
through the MEDIA configuration
signal. The drive impedance is 50
Ω
when MEDIA is low and 75
Ω
when high.