MOTOROLA
Chapter 7. Electrical Specifications and Characteristics
7-7
AC Electrical Characteristics
7.3.2.1
Receiver Interface, Non-DDR Timing
The following sections provide the receiver, non-DDR timing specifications for the
MC92603.
7.3.2.1.1
Receiver, Non-DDR Clock Timing (All Modes Except Ethernet TBI
Modes)
Figure 7-3 provides the receiver interface, non-DDR timing diagram when TBIE is negated
low or COMPAT is negated low.
Figure 7-3. Receiver, Non-DDR Timing Diagram (TBIE = Low or COMPAT = Low)
Table 7-7 provides the receiver, non-DDR timing specifications when TBIE is negated low
or COMPAT is negated low.
Table 7-7. Receiver, Non-DDR Timing Specifications
(TBIE = Low or COMPAT = Low)
Symbol
Characteristic
1
1
10 pF output load.
Aligned Clock
Centered Clock
Unit
Note
Min
Max
Min
Max
T
1
Output valid time before rising edge of
RECV
_x_
RCLK
–0.500
0.500
3.500
—
ns
2
2
Full-speed, HSE = low.
–1.000
1.000
7.500
—
ns
3
3
Half-speed, HSE = high.
T
2
Output valid time after rising edge of
RECV
_x_
RCLK
7.000
—
3.500
—
ns
15.000
—
7.500
—
ns
T
3
RECV_x_RCLK cycle time
7.800
8.200
7.800
8.200
ns
15.800
16.200
15.800
16.200
ns
T
1
T
2
RECV_x_RCLK
RECV_x_7-0
RECV_x_K
RECV_x_DV
RECV_x_ERR
RECV_x_COMMA
T
3
Summary of Contents for MC92603
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