Motorola MC92603, Reference Manual

Page: 99 / 134

MOTOROLA Chapter 7. Electrical Specifications and Characteristics 7-9
AC Electrical Characteristics
7.3.2.2 Receiver Interface, DDR Timing
The following sections provides the receiver, DDR timing specifications for the MC92603.
7.3.2.2.1 Receiver, DDR Clock Timing (All Modes Except Ethernet RTBI
Modes)
Figure 7-5 provides the receiver interface DDR timing diagram when TBIE is negated low
or COMPAT is negated low.
Figure 7-5. Receiver, DDR Timing Diagram (TBIE = Low or COMPAT = Low)
Table 7-9 provides the receiver, DDR timing specifications when TBIE is negated low or
COMPAT is negated low.
Table 7-9. Receiver, DDR Timing Specification (TBIE = Low or COMPAT = Low)
Symbol Characteristic
1
1
10 pF output load.
Aligned Clock Centered Clock
Unit Note
Min Max Min Max
T
1
Output valid time before rising/falling edge of
RECV_x_RCLK –0.500 0.500 1.440 — ns
2
2
Full speed, HSE = low.
–1.000 1.000 3.440 — ns
3
3
Half speed, HSE = high.
T
2
Output valid time after rising/falling edge of
RECV_x_RCLK 3.000 — 1.420 — ns
2
7.000 — 3.500 — ns
3
T
3
RECV_x_RCLK cycle time 7.800 8.200 7.800 8.200 ns
2
15.800 16.200 15.800 16.200 ns
3
T
4
RECV_x_RCLK half cycle time 3.800 4.200 3.800 4.200 ns
2
7.800 8.200 7.800 8.200 ns
3
T
1
T
2
RECV
_x_
3–0
RECV
_x_
ERR
RECV
_x_
DV
RECV
_x_
COMMA
T
1
T
2
RECV
_x_
RCLK
T
3
T
4