162
8 MULTIPLE CPU SYSTEM FUNCTIONS
8.4 Data Communication Between CPU Modules
■
Communication through direct access (when C Controller module is on the receiving side)
When the CPU number-based data assurance is enabled, the data is assured.
The data is written from the program.
At the multiple CPU synchronous interrupt program (I45) execution, the data is written.
*1
At the multiple CPU synchronous interrupt program (I45) execution, the data is read.
At the multiple CPU synchronous interrupt program (I45) execution, the data is refreshed.
The data read completion from each CPU is notified to the CPU No.1.
*1 The update to the following data is not performed until the notification of the data read completion is received from other CPUs (No.2 to
No.4).
Ò
Ó
Ô
Õ
Ö
Ô
Ô
Õ
Ö
Ö
SM400
DINC
D0
Fixed cycle
communication
area
Device
Device
Device
Device
Without
refresh
function
Programmable controller CPU
(CPU No.1)
Programmable controller CPU
(CPU No.3)
Programmable controller CPU
(CPU No.4)
C Controller module
(CPU No.2)
Notifies the contents equivalent to
read completion in each refresh cycle.
Fixed cycle
communication
area
Fixed cycle
communication
area
Fixed cycle
communication
area
Summary of Contents for MELSEC iQ-R C R12CCPU-V
Page 1: ...MELSEC iQ R C Controller Module User s Manual Application R12CCPU V ...
Page 2: ......
Page 23: ...1 EXECUTING PROGRAMS 1 3 I O Access Timing 21 1 MEMO ...
Page 32: ...30 3 MEMORY CONFIGURATION OF C Controller Module 3 4 Files MEMO ...
Page 257: ...I 255 MEMO ...
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