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8 MULTIPLE CPU SYSTEM FUNCTIONS
8.4 Data Communication Between CPU Modules
■
Prevention of 64-bit data inconsistency
To avoid 64-bit data inconsistency, access the specified start address of the CPU buffer memory in multiples of four similarly
to the device to be specified.
Checking memory configuration
Memory configuration can be checked with CW Configurator.
[System Parameter]
[Multiple CPU Setting]
[Communication Setting between CPU]
[CPU Buffer Memory
Setting]
[<Detailed Setting>]
Window
Displayed items
Item
Description
Setting
range
Default
[Setting] button in each refresh area
Click the button to configure the refresh settings used for data
communication between CPU modules.
0 points
[Send/Receive Direction Display between
CPUs] button
Click the button to display the arrow that indicates the send/receive
direction.
D8
D12
D0
HG1000
HG1004
HG1010
Device
Data is assured.
Fixed cycle communication area
4 words (64 bits)
Address of a multiple of 4
4 words (64 bits)
4 words (64 bits)
Address that is not a multiple of 4
Data is not assured.
4 words (64 bits)
Summary of Contents for MELSEC iQ-R C R12CCPU-V
Page 1: ...MELSEC iQ R C Controller Module User s Manual Application R12CCPU V ...
Page 2: ......
Page 23: ...1 EXECUTING PROGRAMS 1 3 I O Access Timing 21 1 MEMO ...
Page 32: ...30 3 MEMORY CONFIGURATION OF C Controller Module 3 4 Files MEMO ...
Page 257: ...I 255 MEMO ...
Page 261: ......