MiTAC 8575A, Service Manual

Page: 97 / 219

96
8575
8575
A N/B Maintenance
A N/B Maintenance
Host BUS Interface Continue
Name Pin Attr Signal Description
HPCOMP
I
M GTL P-MOS Compensation Input
HVREF[4:0]
HNCOMPVREF I
M AGTL+ I/O reference voltage
DRAM Controller
Name Pin Attr Signal Description
SDCLK
I
3.3V - M SDRAM Clock Input
SDRCLKI
I
2.5V/3.3V - M SDRAM Read Clock Input
FWDSDCLKO
O
2.5V/3.3V – M
SDRAM Forward Clock Output
MA[14:0]
O
2.5V/3.3V - M System Memory Address Bus
SRAS#
O
2.5V/3.3V - M SDRAM Row Address Strobe
SCAS#
O
2.5V/3.3V - M SDRAM Column Address Strobe
SWE#
O
2.5V/3.3V - M SDRAM Write Enable
CS[5:0]#
CSB[5:0]# O
2.5V/3.3V - M SDRAM Chip Select
CSB[5:0] multiplexed with DQS[5:0]
DQM[7:0]#
O
2.5V/3.3V - M SDRAM Input/Output Data Mask
DQS[7:0]
I/O
2.5V/3.3V - M DDR Data Strobe
MD[63:0]
I/O
2.5V/3.3V - M System Memory Data Bus
CKE[5:0]
O (open-drain)
2.5V/3.3V –
AUX SDRAM Clock Enable
S3AUXSW#
(CKE6)
O (open-drain)
2.5V/3.3V -
AUX Aux power switch for ACPI-S3 state, low active.
DDRVREF[A:B] I
M DDR I/O Reference Voltage
SiS MuTIOL Interface
AIRDY#
I/O
1.5V/3.3V - M AGP Initiator Ready
ATRDY#
I/O
1.5V/3.3V - M AGP Target Ready
ASTOP#
I/O
1.5V/3.3V - M AGP Stop#
ADEVSEL#
I/O
1.5V/3.3V - M AGP Device Select
ASERR#
I
1.5V/3.3V - M
AGP System Error
AREQ#
I
1.5V/3.3V - M AGP Bus Request
AGNT#
O
1.5V/3.3V - M AGP Bus Grant
AAD[31:0]
I/O
1.5V/3.3V - M AGP Address/Data Bus
Name Pin Attr Signal Description
ZCLK
I
3.3V - M SiS MuTIOL Connect
ZUREQ/ZD
REQ I/O
1.8V - M SiS MuTIOL Connect Control pins
ZSTB[1:0]
I/O
1.8V - M SiS MuTIOL Connect Strobe
ZSTB[1:0]#
I/O
1.8V - M
Strobe Compliment
ZAD[15:0]
I/O
1.8V - M I/O
1.8V - M
ZVREF
I
M SiS MuTIOL Connect Reference Voltage
ZCMP_N
I
M N-MOS Compensation Input
ZCMP_P
I
M P-MOS Compensation Input
AGPCLK
I
3.3V – M
AGP Clock
AFRAME#
I/O
1.5V/3.3V - M AGP Frame#
5.2 SiS650 IGUI Host/Memory Controller