99
8575
8575
A N/B Maintenance
A N/B Maintenance
Test Mode/Hardware Trap/Power Management
Name
Pin Attr
Signal Description
DLLEN#
I/O
3.3V/5V - M
Hardware Trap pin (refer to section 5)
DRAM_SEL
I
3.3V/5V - AUX
Hardware Trap pin (refer to section 5)
TRAP[1:0]
I
3.3V/5V - M
Hardware Trap pins (refer to section 5)
ENTEST
I
3.3V/5V - M
Test Mode enable pin
TESTMOD
E[2:0]
I
3.3V/5V - M
Test Mode select pin
Nand Tree Test: 100
AUXOK
I
3.3V - AUXI
Auxiliary Power OK :
This signal is supplied from the power source of resume well. It
is also used to reset the logic in resume power well. If there is
no auxiliary power source on the system, this pin should be tied
together with PWROK.
PCIRST#
I
3.3V - AUXI
PCI Bus Reset :
PCIRST# is supplied from SiS MuTIOL Media IO SiS961.
PWROK
I
3.3V - AUXI
Main Power OK :
A high-level input to this signal indicates the power being
supplied to the system is in stable operating state. During the
period of PWROK being low, CPURST and PCIRST# will all
be asserted until after PWROK goes high for 24 ms.
5.2 SiS650 IGUI Host/Memory Controller
