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8575
8575
A N/B Maintenance
A N/B Maintenance
5.5 PCI1410GGU PCMCIA Controller
PCI Address and Data
Name I/O
Description
AD[31:0]
I/O
PCI address/data bus. These signals make up the multiplexed PCI address
and data bus on the primary interface. During the address phase of a
primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other
destination information. During the data phase, AD31–AD0 contain data.
C/BE#[3:0]
I/O
PCI bus commands and byte enables. These signals are multiplexed on the
same PCI terminals. During the address phase of a primary bus PCI cycle,
C/BE#3–C/BE#0 define the bus command. During the data phase, this 4-bit
bus is used as byte enables. The byte enables determine which
byte paths of
the full 32-bit data bus carry meaningful data. C/BE#0 applies to byte 0
(AD7–AD0),
C/BE#1 applies to byte 1 (AD15–AD8), C/BE2 applies to
byte 2 (AD23–AD16), and C/BE#3 applies
to byte 3 (AD31–AD24).
PAR
I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates
even parity across the AD31–AD0 and C/BE#3–C/BE#0 buses. As an
initiator during PCI cycles, the PCI1410 outputs this
parity indicator with a
one-PCLK delay. As a target during PCI cycles, the calculated parity is
compared to the initiator’s parity indicator. A compare error results in the
assertion of a parity error (PERR#).
16-Bit PC Card Address and Data (Slots A and B)
Name I/O
Description
ADDR[25:0]
O
PC Card address. 16-bit PC Card address lines. ADDR25 is the most
significant bit.
DATA[15:0]
I/O
PC Card data. 16-bit PC Card data lines. DATA15 is the most significant
bit.
Multifunction and Miscellaneous Pins
Name I/O
Description
MFUNC0
I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI
interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV switching
outputs, CardBus audio PWM, GPE#, or a parallel IRQ.
MFUNC1
I/O Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1,
socket activity LED output, ZV switching outputs, CardBus audio PWM,
GPE#, or a parallel IRQ.
Serial data (SDA). When VPPD0 and VPPD1 are high after a PCI reset, the
MFUNC1 terminal provides the SDA signaling for the serial bus interface.
The two-pin serial interface loads the subsystem identification and other
register defaults from an EEPROM after a PCI reset.
MFUNC2
I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA
request, GPI2, GPO2, socket activity LED output, ZV switching outputs,
CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ.
MFUNC3
I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or
the serialized interrupt signal IRQSER.
MFUNC4
I/O Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK#,
GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus
audio PWM, GPE#, RI_OUT#, or a parallel IRQ.
Serial clock (SCL). When VPPD0 and VPPD1 are high after a PCI reset,
the MFUNC4 terminal provides the SCL signaling for the serial bus
interface. The two-pin serial interface loads the subsystem identification and
other register defaults from an EEPROM after a PCI reset.
MFUNC5
I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA
grant, GPI4, GPO4, socket activity LED output, ZV switching outputs,
CardBus audio PWM, GPE#, or a parallel IRQ.
MFUNC6
I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN#
or a parallel IRQ.
RI_OUT#/PME#
O
Ring indicate out and power management event output. Terminal provides
an output for ring-indicate or PME# signals.
SPKROUT
O
Speaker output. SPKROUT is the output to the host system that can carry
SPKR# or CAUDIO through the PCI1410 from the PC Card interface.
SPKROUT is driven as the exclusive-OR combination of card
SPKR#//CAUDIO inputs.
SUSPEND#
I
Suspend. SUSPEND# protects the internal registers from clearing when the
GRST# or PRST# signal is asserted.
