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8575
8575
A N/B Maintenance
A N/B Maintenance
5.5 PCI1410GGU PCMCIA Controller
CardBus PC Card Interface System (Slots A and B)
Name I/O
Description
CCLK
O
CardBus clock. CCLK provides synchronous timing for all transactions on
the CardBus interface. All signals except CRST#, CCLKRUN#, CINT#,
CSTSCHG, CAUDIO, CCD2#, CCD1#, CVS2, and CVS1 are sampled on
the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency,
but it can be stopped in the low state or slowed down for power savings.
CCLKRUN#
I/O CardBus clock run. CCLKRUN# is used by a CardBus PC Card to request
an increase in the CCLK frequency, and by the PCI1410 to indicate that the
CCLK frequency is going to be decreased.
CRST#
O
CardBus reset. CRST# brings CardBus PC Card-specific registers,
sequencers, and signals to a known state. When CRST# is asserted, all
CardBus PC Card signals are placed in a high-impedance state, and the
PCI1410 drives these signals to a valid logic level. Assertion can be
asynchronous to CCLK, but deassertion must be synchronous to CCLK.
CardBus PC Card Address and Data (Slots A and B)
Name I/O
Description
CAD[31:0]
I/O CardBus address and data. These signals make up the multiplexed CardBus
address and data bus on the CardBus interface. During the address phase of
a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data
phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most
significant bit.
CC/BE#[3:0]
I/O CardBus bus commands and byte enables. CC/BE#3–CC/BE#0 are
multiplexed on the same CardBus terminals. During the address phase of a
CardBus cycle, CC/BE#3–CC/BE#0 define the bus command. During the
data phase, this 4-bit bus is used as byte enables. The byte enables
determine which byte paths of the full 32-bit data bus carry meaningful
data. CC/BE#0 applies to byte 0 (CAD7–CAD0), CC/BE#1 applies to byte
1 (CAD15–CAD8), CC/BE#2 applies to byte 2 (CAD23–CAD8), and
CC/BE#3 applies to byte 3 (CAD31–CAD24)
.
CPAR
I/O CardBus parity. In all CardBus read and write cycles, the PCI1410
calculates even parity across the CAD and CC/BE# buses. As an initiator
during CardBus cycles, the PCI1410 outputs CPAR with a one-CCLK
delay. As a target during CardBus cycles, the calculated parity is compared
to the initiator’s parity indicator; a compare error results in a parity error
assertion.
CardBua PC Card Interface Control (Slots A and B)
Name I/O
Description
CAUDIO
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the
system speaker. The PCI1410 supports the binary audio mode and outputs a
binary signal from the card to SPKROUT.
CBLOCK#
I/O
CardBus lock. CBLOCK# is used to gain exclusive access to a target.
CCD1#
CCD2#
I
CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are used in
conjunction with CVS1 and CVS2 to identify card insertion and interrogate
cards to determine the operating voltage and card type.
CE1#
CE2#
O
Card enable 1 and card enable 2. CE1# and CE2# enable even- and
odd-numbered address bytes. CE1# enables even-numbered address bytes,
and CE2# enables odd-numbered address bytes.
CDEVSEL#
I/O
CardBus device select. The PCI1410 asserts CDEVSEL# to claim a
CardBus cycle as the target device. As a CardBus initiator on the bus, the
PCI1410 monitors CDEVSEL# until a target responds. If no target responds
before timeout occurs, then the PCI1410 terminates the cycle with an
initiator abort.
CFRAME#
I/O
CardBus cycle frame. CFRAME# is driven by the initiator of a CardBus bus
cycle. CFRAME# is asserted to indicate that a bus transaction is beginning,
and data transfers continue while this signal is asserted. When CFRAME# is
deasserted, the CardBus bus transaction is in the final data phase.
CGNT#
O
CardBus bus grant. CGNT# is driven by the PCI1410 to grant a CardBus
PC Card access to the CardBus bus after the current data transaction has
been completed.
CINT#
I
CardBus interrupt. CINT# is asserted low by a CardBus PC Card to request
interrupt servicing from the host.
CIRDY#
I/O
CardBus initiator ready. CIRDY# indicates the CardBus initiator’s ability to
complete the current data phase of the transaction. A data phase is
completed on a rising edge of CCLK when both CIRDY# and CTRDY# are
asserted. Until CIRDY# and CTRDY# are both sampled asserted, wait
states are inserted.
