100
8575
8575
A N/B Maintenance
A N/B Maintenance
Host Bus Interface
Name
Pin Attr
Signal Description
FERR#
I
1.1V/2.65V -M
Floating Point Error:
CPU will assert this signal upon a floating point error occurring.
IGNNE#
OD
1.1V/2.65V -M
Ignore Numeric Error:
IGNNE# is asserted to inform CPU to ignore a numeric error.
NMI
OD
1.1V/2.65V -M
Non-Maskable Interrupt:
A rising edge on NMI will trigger a non-maskable interrupt to
CPU.
INTR
OD
1.1V/2.65V -M
Interrupt Request:
High-level voltage of this signal conveys to CPU that there is
outstanding interrupt(s) needed to be serviced.
APICD[1:0]
I/OD
1.1V/2.65V -M
APIC Data:
These two signals are used to send and receive APIC data.
CPUSLP#/
CPUSTP#
OD
1.1V/2.65V -M
CPU Sleep:
The CPUSLP# can be used to force CPU enter the Sleep state.
CPU Clock STOP:
For Intel Mobile processor, this signal can be used to stop the
clock to the processor. If the processor is in Quick Start state
and the processor clock is stopped, the processor will enter the
Deep Sleep state.
For AMD processor, this signal can be to reduce processor
voltage during C3/S1 state.
STPCLK#
OD
1.1V/2.65V -M
Stop Clock:
STPCLK# will be asserted to inhibit or throttle CPU activities
upon a pre-defined power management event occurs
INIT#
OD
1.1V/2.65V -M
Initialization:
INIT is used to re-start the CPU without flushing its internal
caches and registers. In Pentium III platform it is active high.
This signal requires an external pull-up resistor tied to 3.3V.
APICCK
I
2.5V - M
APIC Clock:
This signal is used to determine when valid data is being sent
over the APCI bus.
A20M#
OD
1.1V/2.65V- M
Address 20 Mask:
When A20M# is asserted, the CPU A20 signal will be
forced to “0”
MuTIOL Connect Interface
Name
Pin Attr
Signal Description
ZCLK
I
3.3V - M
Megaband I/O Connect Clock
ZUREQ
I/O
1.8V - M
Megaband I/O Conect Controll pins
ZDREQ
I/O
1.8V - M
Megaband I/O Conect Controll pins
ZSTB[1:0]
I/O
1.8V - M
Megaband I/O Connect Strobe
ZSTB[1:0]#
I/O
1.8V - M
Strobe Compliment
ZAD[15:0]
I/O
1.8V - M
Address/Data pins
ZVRE
I -M
Megaband I/O Connect I/O reference voltage
ZCMP_N
I -M
N-MOS Compensation Input
ZCMP_P
I -M
P-MOS Compensation input
PCI Interface
Name
Pin Attr
Signal Description
PCICLK
I
3.3V/5V -M
PCI Clock:
The PCICLK input provides the fundamental timing and the
internal operating frequency for the SiS961. It runs at the same
frequency and skew of the PCI local bus.
C/BE[3:0]#
I/O
3.3V/5V -M
PCI Bus Command and Byte Enables:
PCI Bus Command and Byte Enables define the PCI command
during the address phase of a PCI cycle, and the PCI byte
enables during the data phases. C/BE[3:0]# are outputs when the
SiS961 is a PCI bus master and inputs when it is a PCI slave.
PLOCK#
I/O
3.3V/5V -M
PCI Lock:
When PLOCK# is sampled asserted at the beginning of a PCI
cycle, SiS961 considers itself being locked and remains in the
locked state until PLOCK# is sampled and negated at the
following PCI cycle.
5.3 SiS961 MuTIOL Media I/O Controller
