Hardware Overview
Theory of Operation
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0070-10-0591-01
Trio™ Service Manual
Display
The resolution is 800 x 600. Frequency is 38 MHz. It works in an appropriate SVGA mode.
VRAM adopts 16-bit structure and is divided into an alphanumeric character screen and a
waveform screen. To the left of the alphanumeric character screen is the corresponding
waveform screen. The character screen is used to display data and flashing alarming
parameters. The user can select the color of the waveform and alphanumeric characters for
each parameter.
LVDS Interface
By utilizing time-share sampling, the LVDS (Low Voltage Differential Signaling) interface
converts multi-channel CMOS/TTL signals into single channel, low-voltage, double-frequency
differential signals. LVDS interface is generally realized by a special integrated circuit. The
special LVDS chip used for display is DS90CF363A. This chip converts 18-bits of RGB data
and 3 bits of LCD timing and control data (21 bits of CMOS/TTL data) into 3 LVDS data
streams. Four differential signals including the 3 data streams and a phase-locked frequency
are transmitted to the display screen. The working frequency of DS90CF363A is 20~65
MHz.
Reset and Parameter Storage
The CPU board uses an integrated chip CAT1161, which controls both power-on reset and
parameter storage. This chip has an E2PROM with the capacity of 2K. It can be used to
modify and store various nonvolatile parameters of the host. The power-on reset and
WATCHDOG functions are used to realize reset function of the CPU board. When J1 is open
circuit, the software can also disable WATCHDOG by using the output signal PP0 of CPU in
order to realize the self test of WATCHDOG. The bus interface of this chip is I2C.
Network Controller
The network controller adopts special chip AX88796. Its working clock is 25 MHz. It also
has internal 16 K high-speed buffer SRAM. The data bus of this chip is 16-bit width.
Key Test Points
NO.
NAME FUNCTION
1
V33
Digital supply voltage: +3.3 V
2
V25
FPGA supply voltage: +2.5 V
3
V3
Lithium battery voltage: +3 V
4
CLK
CPU master clock: 54 MHz
5
PCK
FPGA and display clock: 38 MHz
6
NCK
Network chip clock: 25 MHz
7
/RST
System reset signal
8
/NINT
Network chip interrupt signal
9
DO
Signal indicating successful FPGA configuration
