Mindray PM-7000, Service Manual

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Chapter 2 Principles
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In addition, FPGA also extends multiple serial ports, which communicate with peripheral
modules. FPGA transfers the received data to CPU through the bus; CPU delivers data to
FPGA through the bus, and then the FPGA transfers those data to the peripheral
modules.
Watchdog
When powered on, watchdog provides reset signals for CPU, FPGA and Ethernet
Controller.
The patient monitor provides the watchdog timer output and voltage detection functions.
2.2.2 ECG/RESP/TEMP Module
2.2.2.1 General
This module provides the function of measuring three parameters: electrocardiograph (ECG),
respiration (RESP) and temperature (TEMP).
2.2.2.2 Principle diagram
Figure 2-5 Working principle of the ECG/RESP/TEMP module
2.2.2.3 Principle
This module collects the ECG, RESP and TEMP signals through the transducer, processes the
signals, and sends the data to the main board through the serial port.
ECG Signal Input Circuit
The input protection and filtering circuits receive the ECG signal from the transducer, and filter
the high-frequency interference signal to protect the circuit against the damage by defibrillator
high-voltage and ESD.
The right-leg drive circuit gets the 50/60Hz power common-mode signal from the lead cable,
and sends the negative feedback signal to the human body to reject the common-mode
interference signal on the lead cable, which helps the detection of the ECG signal.
The lead-off detecting circuit checks whether the ECG lead is off, and sends the information to
CPU.
ECG Signal Process Circuit
The difference amplifying circuit conducts the primary amplification of the ECG signal and