RTE-V830-PC
USER’ S MANUAL
34
11.9. 32-BIT BUS MODE (BURST READ, INTERLEAVE)
The following timing chart shows the waveforms that occur when a DRAM area row address to
be accessed in a burst read cycle in the 32-bit bus interleave mode matches (hit) a row address
used in the previous cycle.
If the row address does not match (mishit) the previous one or is the first one after a refresh
cycle, the beginning section of the cycle differs from the one shown in the following timing chart.
It is the same as in the single read cycle. See the descriptions about the single read cycle.
²
The waveform width indicated as Nclk (*1) in the timing chart corresponds to the number of
clock cycles in the read CAS width (1 to 3) to be specified for the port. The minimum
cycle is in the 3-1-1-1 format.
²
64 bits of data are read at a time. The lower 32 bits are passed to the CPU at the first data
sampling, and the upper 32 bits are passed to the CPU on the next clock cycle. (*2)
²
The RAS- signal is kept at a low level for page mode access even after the end of the cycle.
(*3)
WE-
CASH-
CASL-
*2
*2
*2
*2
*3
Low
Nclk
*1
Nclk
*1
HIT
RAS-
Sig1: A2 to A27, BE0- to BE3-, ST0 to ST3
Sig1
D0 to D31
READY-
BCYST-
BCLK
