RTE-V830-PC
USER’ S MANUAL
29
11.4. 32-BIT BUS MODE (SINGLE READ, HIT)
The following timing chart shows the waveforms that occur when a row address to be accessed
in a single read cycle during the 32-bit bus mode matches (hit) a row address used in the
previous cycle.
²
The waveform width indicated as Nclk (*1) in the timing chart corresponds to the number of
clock cycles in the read CAS width (1 to 3) to be specified for the port. The minimum
cycle is one wait state.
²
The RAS- signal is kept at a low level for page mode access even after the end of the cycle.
(*2)
²
The upper and lower 32-bit banks are read simultaneously. The CPU is supplied with
data from an appropriate bank according to the state of A2.
WE-
CASH-
CASL-
*2
Low
Nclk
*1
HIT
RAS-
Sig1: A2 to A27, BE0- to BE3-, ST0 to ST3
Sig1
D0 to D31
READY-
BCYST-
BCLK
