RTE-V830-PC
USER’ S MANUAL
41
11.15. 16-BIT BUS MODE (BURST READ, INTERLEAVE)
The following timing chart shows the waveforms that occur when a DRAM area row address to
be accessed in a burst read cycle during the 16-bit bus interleave mode matches (hit) a row
address used in the previous cycle.
If the row address does not match (mishit) a row address used in the previous cycle or is the first
one after a refresh cycle, only the beginning section of the cycle differs from the one in the 32-
bit bus mode. See the descriptions about the single read cycle in the 32-bit bus mode.
²
The waveform width indicated as Nclk (*1) in the timing chart corresponds to the number of
clock cycles in the read CAS width (1 to 3) to be specified for the port. The minimum
cycle is in the 3-1-1-1-1-1-1-1 format.
²
64 bits of data are read at a time. Groups of 16 bits are passed to the CPU sequentially
starting at the lowest group. (*2)
²
The RAS- signal is kept at a low level for page mode access even after the end of the cycle.
(*3)
WE-
CASH-
CASL-
*2
*2
*2
*2
*2
*2
*2
*2
*3
Low
Nclk
*1
RAS-
Sig1: A2 to A27, BE0- to BE3-, ST0 to ST3
D0 to D15
Sig1
READY-
BCYST-
BCLK
HIT
Nclk
*1
Nclk-1
*1
Nclk-1
*1
