RTE-V830-PC
USER’ S MANUAL
27
11. APPENDIX DRAM TIMING
11.1. DRAM INTERFACE OVERVIEW
The DRAM consists of two 32-bit banks. In the ordinary mode (interleave mode), the banks are
accessed alternately so that the access time during burst access can be reduced.
The DRAM is accessed in the page mode. The RAS signal for the DRAM is kept active as long
as the same row address is being accessed; access is controlled only by manipulating the CAS
signal. This method can reduce the access time if access continues with the same row
address.
11.2. SIGNAL DESCRIPTIONS
The signals used for waveforms described in this chapter are defined as follows:
BCLK:
Bus clock pulse input to the CPU
BCYST-: Bus cycle start signal output from the CPU
READY-: Ready signal input to the CPU
HIT:
Signal that indicates whether a row address is the same as one used in the previous
cycle, because the DRAM is used in the page mode. This signal is generated by the
DRAM control circuit.
RAS-:
RAS signal input to the DRAM
CASL-: CAS signal input to the lower 32-bit bank of DRAM. One CASL- signal is provided
for each byte in the word (hence, CASL0 to CASL3-)
CASH-: CAS signal input to the upper 32-bit bank of DRAM. One CASH- signal is provided
for each byte in the word (hence, CASH0 to CASH3-)
WE-:
WE signal input to the DRAM
