RTE-V830-PC
USER’ S MANUAL
18
PRCWIDE1..0: These bits specify the precharge width for DRAM operations.
PRCWIDE1
PRCWIDE0
Function
0
0
This bit combination shall not be specified.
0
1
The precharge width is specified to be one CPU bus clock
cycle.
1
0
The precharge width is specified to be two CPU bus clock
cycles.
1
1
The precharge width is specified to be three CPU bus clock
cycles.
Port 2: Internal control port (output).....61000808h
P23
P22
P21
P20
DTR-
NMIMASK TOVERFCLR-
Reserved
field 1
Reserved field 1: The bit in this field is reserved for the system. Once the bit is initialized to 1,
do not change it.
TOVERCLR-:
This is a control bit used to clear TOVERF- in bit 5 of port 2. It should be
initialized to 1 and usually kept to be 1. When TOVERF- is to be cleared,
the bit should be rest to 0, then set back to 1.
NMIMASK:
This bit is used to mask an NMI signal input to the CPU. When the bit is 1,
the NMI signal is masked at a gate. The bit should be initialized to 1.
When an NMI becomes acceptable, the bit should be reset to 0. In the Multi
monitor, it is initialized to 1.
DTR-:
This bit controls the DTR signal output from the JSIO connector. The
inverted state of this bit is converted to the RS-232C level and output to the
JSIO connector.
Port 2: Internal control port (input).....61000808h
P27
P26
P25
P24
PD2
PD1
TOVERF-
DSR-
DSR-:
This bit indicates the state of the DSR signal input from the JSIO connector. The
state of this bit represents the inverted state of the DSR signal at the JSIO
connector.
TOVERF-: This bit becomes 0, when 30 or more bus cycles occur to result in a time-out. The
flag is cleared (to 1), using bit 1 (TOVERCLR-) of port 2.
PD[2..1]:
PD[2..1] of a DRAM (72-pin SIMM) chip mounted on the board can be read-
accessed. The states of these bits indicate the size of the DRAM area. The
following table lists the relationships between PD[2..1] and the DRAM capacity.
