RTE-V830-PC
USER’ S MANUAL
28
11.3. 32-BIT BUS MODE (SINGLE READ, NORMAL)
The following timing chart shows the waveforms that occur when an area is accessed in a single
read cycle during the 32-bit bus mode for the first time after a reset or when the area is accessed
after the precharge time has elapsed since the end of a refresh cycle (normal).
²
The waveform widths indicated as Mclk (*1) and Nclk (*2) in the timing chart correspond to
the number of clock cycles in the RAS width (2 to 4) and read CAS width (1 to 3) to be set
for the port, respectively. The minimum cycle is one wait state.
²
The RAS- signal is kept at a low level for page mode access even after the end of the cycle.
(*3)
²
The upper and lower 32-bit banks are read simultaneously. The CPU is supplied with
data from an appropriate bank according to the state of A2.
WE-
CASH-
CASL-
*3
Nclk
*2
Mclk
*1
HIT
RAS-
Sig1: A2 to A27, BE0- to BE3-, ST0 to ST3
Sig1
D0 to D31
READY-
BCYST-
BCLK
