PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
3
2.2
Prerequisites
Before you start:
1.
Download the reference design files from:
http://soc.microsemi.com/download/rsc/?f=mpf_dg0799_eval_liberosocv12p1_df
2.
Download and install Libero SoC v12.1 on the host PC from
https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads
3.
The latest versions of ModelSim and Synplify Pro are included in the Libero SoC PolarFire
installation package. Make sure you have a Libero Gold license for design evaluation on MPF300
device. A one year Gold software License is included with the Evaluation kit.
4.
If you already purchased a Gold license and received a Software ID from Microsemi, generate your
Gold License using the following link:
https://soc.microsemi.com/portal/default.aspx?r=1
5.
Download Cat Karat and Wireshark.
2.3
Demo Design
The following is the data flow for the 1G Ethernet loopback demo design:
1.
PF_CCC_0 provides the clock to the Mi-V processor and other APB peripherals.
2.
PF_IOD_CDR_CCC_C0 generates:
•
The fabric transmit clock ((TX_CLK_G)) for the CoreTSE block.
•
The high-speed bank clocks, and drives the high-speed clocks (HS_IO_CLKs) of the
PF_IOD_CDR_C0 block for clock recovery.
3.
PF_IOD_CDR_CCC_C0 also generates Delay codes for the PVT compensation.
4.
Mi-V performs the following functions:
•
Executes the application from LSRAM (PF_SRAM IP).
•
Configures the ZL30364 clock generation hardware through the CoreSPI IP to generate
reference clocks for the VSC PHY and the IOD CDR fabric module.
•
Configures the Management registers of CoreTSE and VSC PHY.
•
Sends a request to the CoreTSE IP to negotiate with the on-board VSC8575 PHY.
5.
CoreTSE IP implements 1G Ethernet MAC and is configured in ten bit interface mode (TBI) to
interface with the PF_IOD_CDR_C0. The CoreTSE IP has an inbuilt MDIO interface to exchange
control and status information with the VSC PHY.
6.
PF_IOD_CDR IP does the following:
•
Interfaces with the on-board VSC8575 PHY and forms the SGMII link.
•
Recovers the data and clock from the incoming RX_P and RX_N ports.
•
Sends the recovered clock (RX_CLK_R) to the CoreTSE block.
•
Deserializes the recovered data and sends 10-bit parallel data to CoreTSE.
•
Receives Ethernet data via the RX_P and RX_N input pads, gears down the receive data rate,
and deserializes the data.
•
The deserialized data is sent from PF_IOD_CDR_C0:RX_DATA[9:0] to CoreTSE IP: RCG[9:0].
•
The received data is looped back at the CoreTSE IP, and CoreTSE IP:TCG[9:0] is sent to
PF_IOD_CDR_C0:TX_DATA[9:0].
•
PF_IOD_CDR_C0 serializes the data, gears up the transmit data rate, and transmits the data to
the on-board VSC PHY via the TX_P and TX_N output pads.
page 4 shows the hardware implementation of the demo design.
Libero SoC Design Suite
v12.1
Table 1 •
Design Requirements
(continued)
Requirement
Version
