Appendix: Multi-Lane 1G IOD CDR Design
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
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Appendix: Multi-Lane 1G IOD CDR Design
In a multi-lane design, Ethernet traffic from multiple RJ45 cables, comes into the FPGA via PHY. In such
cases, multiple RX and TX ports must be assigned from the PolarFire GPIO Banks to form multiple
SGMII links with the PHY. The following figure shows the placement of I/O Banks and PLLs in a PolarFire
device (MPF300).
Figure 35 •
I/O Banks and PLL placement in MPF300
Each Bank has multiple I/O Lanes and each I/O Lane includes 6 I/O pairs. The lane controller available in
each I/O lane has a clock recovery unit, which is used for the Clock recovery of that lane. Hence, only
one SGMII link can be realized from an I/O lane.
For an 8-lane design, 8 I/O Lanes are used to form 8 SGMII links. To enable sharing of the
PF_IOD_CDR_CCC, the selection of these I/O Lanes must be made in any of the following ways:
•
Lanes of the same Bank can be selected vertically upto half of the side
•
Lanes of the same Bank can be selected horizontally upto half of the side
•
Lanes from vertical and horizontal Banks can be selected
Note:
In Libero SoC, when I/O lanes are selected from Bank 5 or 2, or from both and placed, the
PF_IOD_CDR_CCC selects the SW PLL and is placed SW. If all I/O lanes are selected from Bank 4,
PF_IOD_CDR_CCC selects the NW PLL and is placed NW.
When the reference clock for all the links is same:
•
PF_IOD_CDR_CCC can be shared across all IOD blocks (PF_IOD_CDR) for the HSIO BANK
clocks and transmit clock (TX_CLK).
•
PF_IOD_CDR_CCC uses an internal lane controller to generate the DLL delay code and shares it
with all IOD blocks. The DLL delay code is required for phase tuning/adjustment.
GPIO
Bank 5
T
ransceiv
er Lane
16-24 Lanes
NW
Corner
GPIO
Bank 4
HSIO
Bank 1
HSIO
Bank 7
HSIO
Bank 0
NE
Corner
SW
Corner
SE
Corner
HSIO
Bank 6
GPIO
Bank 2
JTAG/SPI
Bank 3
