PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
12
2.3.3.12 Design Memory Map
page 12 shows the Mi-V processor bus interface memory map.
Figure 11 •
Mi-V Processor Bus Interface Memory Map
2.3.3.13 CoreAHBLite_0
CoreAHBLite_0 is configured as shown in
page 13 to interface the PF_SRAM for accessing
the LSRAM at memory address 0x8000_0000. This configuration is required because the Mi-V processor
executes the code from 0x8000_0000.
