Libero Design Flow
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
19
1.
On the
Design Flow
tab
,
double-click
Verify Timing
.
When the design successfully meets the timing requirements, a green tick mark appears next to
Ver-
ify Timing
, as shown in
2.
Right-click
Verify Timing
and select
View Report
to view the verify timing report and log files in the
Reports
tab.
3.4
Generate FPGA Array Data
On the
Design Flow
tab, double-click
Generate FPGA Array Data
.
When the FPGA array data is successfully generated, a green tick mark appears next to
Generate
FPGA Array Data
, as shown in
