Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
36
For other XCVR ports, see
UG0677: PolarFire FPGA Transceiver User Guide
CLKS_FROM_TX_PLL
XCVR transmit clock sourced from the
TX PLL.
LANE0_RXD_N
LANE0_RXD_P
Differential receive input pads for
receiving the Ethernet data.
LANE0_CDR_REF_CLK
125 MHz reference for clock and data
recovery.
LANE0_PCS_ARST_N
Asynchronous active-low reset signal
used to reset the PCS module of
XCVR lane.
LANE0_PMA_ARST_N
Asynchronous active-low reset signal
used to reset the PMA module of
XCVR lane.
LANE0_RX_DATA[9:0]
The 10-bit RX data from XCVR to
CoreTSE:RCG[9:0].
LANE0_TXD_N
LANE0_TXD_P
Differential transmit output pads.
LANE0_RX_CLK_R
Recovered regional receive clock from
XCVR to the fabric logic and
CoreTSE:TBI_RX_CLK.
LANE0_TX_DATA[9:0]
The 10-bit TX data from
CoreTSE:TCG[9:0] to XCVR.
Table 7 •
XCVR Port Connections
(continued)
Port Name
Input or Output
Connection Description
