MEIG SLM500, Hardware Design Manual

Page: 14 / 78

MeiG Smart product technical information
SLM500
Hardware Design Guide
Page 14
250
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255
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256
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261
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266
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268
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269
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271~274
display interface (MIPI)
MIPI_DSI0_CLK_M 52 I/O
MIPI_LCD clock
MIPI_DSI0_CLK_P
53 I/O
MIPI_DSI0_LANE0_M 54 I/O
MIPI_LCD data
MIPI_DSI0_LANE0_P 55 I/O
MIPI_DSI0_LANE1_M 56 I/O
MIPI_DSI0_LANE1_P 57 I/O
MIPI_DSI0_LANE2_M 58 I/O
MIPI_DSI0_LANE2_P 59 I/O
MIPI_DSI0_LANE3_M 60 I/O
MIPI_DSI0_LANE3_P 61 I/O
GPIO61_LCD_RST_N 49 O LCD reset
GPIO24_LCD_TE0 50 I/O LCD frame sync signal
UART(1.8V)
GPIO0_UART1_TXD 154 I
UART1
data transmit
GPIO1_UART1_RXD 153 O
UART1
data receive
GPIO4_DBG_UART_TX 94 I UART2
data receive
GPIO5_DBG_UART_RX 93 O
UART2
data transmit
GPIO16_UART5_TXD 34 I
UART5 data receive
GPIO17_UART5_RXD 35 O
UART5 data transmit
GPIO18_UART5_CTS 36 I UART5 Clear To Send
（
CTS
）
GPIO19_UART5_RTS 37 O
UART5 Request To Send
（
RTS
）
UIM card Interface
GPIO54_UIM1_DET
22
I UIM1 insert detect
UIM1_RESET
23
O
UIM1 reset
UIM1_CLK
24
O
UIM1 clock
UIM1_DATA
25
I/O UIM1 data
GPIO58_UIM2_DET
17
I
UIM2 insert detect
UIM2_RESET
18
O UIM2 reset
UIM2_CLK
19
O UIM2 clock
UIM2_DATA
20
I/O
UIM2 data
Front Camera