MeiG Smart product technical information
SLM500
Hardware Design Guide
Page 36
GPIO1_UART1_RXD
153
O
UART1 Data Reception
GPIO4_DBG_UART_TX
94
I
UART2 Data Transmission
GPIO5_DBG_UART_RX
93
O
UART2 Data Reception
GPIO16_UART5_TXD
34
I
UART5 Data Transmission
GPIO17_UART5_RXD
35
O
UART5 Data Reception
GPIO18_UART5_CTS
36
I
UART5 Clear To Send
（
CTS
）
GPIO19_UART5_RTS
37
O
UART5 Request To Send
（
RTS
）
Please refer to the following connection method:
Figure 4.13
：
Serial Port Connection Diagram
When the serial level used by the user does not match the module, in addition to adding the
level shifting IC, the following figure can also be used to achieve level matching. Only the
matching circuits on TX and RX are listed here. Other low speed signals can refer to this two
circuits.
Figure 4.14
：
TX Connection Diagram
module
