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Maxim DS33Z41 User Manual Download Page 91

DS33Z41 Quad IMUX Ethernet Mapper 

 

 

91 of 167 

 

 
Register Name: 

LI.TIFGC 

Register Description: 

Transmit Inter-Frame Gapping Control Register 

Register Address: 

0C5h 

 
Bit 

# 7 6 5 4 3 2 1 0 

Name  TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFG0 
Default 

0 0 0 0 0 0 0 1 

Bits 7 to 0: Transmit Inter-Frame Gapping (TIFG7 to TIFG0).

 These eight bits indicate the number of additional 

flags and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill 
between packets is at least the value of TIFG[7:0] plus 1. Note: If inter-frame fill is set to all ones, a TFIG value of 
2 or 3 will result in a flag, two bytes of ones, and an additional flag between packets. 
 
 
Register Name: 

LI.TEPLC 

Register Description: 

Transmit Errored Packet Low Control Register 

Register Address: 

0C6h 

 
Bit 

# 7 6 5 4 3 2 1 0 

Name  TPEN7 TPEN6 TPEN5 TPEN4 TPEN3 TPEN2 TPEN1 TPEN0 
Default 

0 0 0 0 0 0 0 0 

Bits 7 to 0: Transmit Errored Packet Insertion Number (TPEN7 to TPEN0).

 These eight bits indicate the total 

number of errored packets to be transmitted when triggered by TIAEI. Error insertion will end after this number of 
errored packets have been transmitted. A value of FFh results in continuous errored packet insertion at the 
specified rate. 

Summary of Contents for DS33Z41

Page 1: ...n increments of 512kbps FUNCTIONAL DIAGRAM FEATURES 10 100 IEEE 802 3 Ethernet MAC MII and RMII Half Full Duplex with Automatic Flow Control Layer 1 Inverse Multiplexing Allows Bonding of Up to 4 T1 E...

Page 2: ...FACE 23 8 1 1 Read Write Data Strobe Modes 23 8 1 2 Clear on Read 23 8 1 3 Interrupt and Pin Modes 23 8 2 CLOCK STRUCTURE 24 8 2 1 Serial Interface Clock Modes 26 8 2 2 Ethernet Interface Clock Modes...

Page 3: ...DEFINITIONS 68 9 3 ARBITER REGISTERS 81 9 3 1 Arbiter Register Bit Descriptions 81 9 4 BERT REGISTERS 82 9 5 SERIAL INTERFACE REGISTERS 89 9 5 1 Serial Interface Transmit and Common Registers 89 9 5 2...

Page 4: ...Z 163 12 2 6 IDCODE 163 12 3 JTAG ID CODES 164 12 4 TEST REGISTERS 164 12 4 1 Boundary Scan Register 164 12 4 2 Bypass Register 164 12 4 3 Identification Register 164 12 5 JTAG FUNCTIONAL TIMING 165 1...

Page 5: ...56 Figure 8 16 CIR in the WAN Transmit Path 59 Figure 10 1 MII Transmit Functional Timing 140 Figure 10 2 MII Transmit Half Duplex with a Collision Functional Timing 140 Figure 10 3 MII Receive Funct...

Page 6: ...9 3 Arbiter Register Bit Map 62 Table 9 4 BERT Register Bit Map 62 Table 9 5 Serial Interface Register Bit Map 63 Table 9 6 Ethernet Interface Register Bit Map 65 Table 9 7 MAC Indirect Register Bit M...

Page 7: ...hernet packets and transmits the extracted packets over the Ethernet port The WAN physical interface is based on the Dallas Semiconductor Interleaved Bus Operation IBO running at 8 192Mbps The IBO int...

Page 8: ...nd maximum 2016 bytes Supports bit stuffing destuffing Selectable packet scrambling descrambling X43 1 Separate FCS errored packet and aborted packet counts Programmable inter frame fill for transmit...

Page 9: ...imum MAC frame size up to 2016 bytes Minimum MAC frame size 64 bytes Discards frames greater than Programmed Maximum MAC frame size and Runt non octet bounded or bad FCS frames upon reception Programm...

Page 10: ...s the specifications and relevant sections that are applicable to the DS33Z41 Table 2 1 T1 Related Telecommunications Specifications IEEE 802 3 2002 CSMA CD access method and physical layer specificat...

Page 11: ...E3 OC 1 EC 1 G SHDSL or HDSL2 4 Refer also to Application Note 3411 DS33Z11 Ethernet LAN to Unframed T1 E1 WAN Bridge for an example of a complete LAN to WAN design Figure 3 1 Quad T1 E1 SCT to DS33Z...

Page 12: ...ng Note 3 The terms Transmit Queue and Receive Queue are with respect to the Ethernet Interface The Receive Queue is the queue for the data that arrives on the MII RMII interface is processed by the M...

Page 13: ...port More information on microprocessor control is available in Section 8 1 6 BLOCK DIAGRAMS Figure 6 1 Detailed Block Diagram MAC RMII MII SDRAM Interface Buffer Dev Div by 2 4 12 Output Clocks 25 50...

Page 14: ...receive serial data on RSER Gapped clocking is supported up to the maximum RCLKI frequency of 52MHz RSER H1 I Receive Serial Data Input Receive Serial data arrives on the rising edge of the clock RSYN...

Page 15: ...input provided by the PHY In DCE mode this is an output derived from REF_CLK providing 2 5MHz 10Mbps operation or 25MHz 100Mbps operation RXD 0 RXD 1 RXD 2 RXD 3 B11 C11 D11 A11 I Receive Data 0 throu...

Page 16: ...Bit 4 Address bit 4 of the microprocessor interface A5 A3 I Address Bit 5 Address bit 5 of the microprocessor interface A6 B3 I Address Bit 6 Address bit 6 of the microprocessor interface A7 C3 I Add...

Page 17: ...active state is programmable in register GL CR1 is deasserted when all interrupts have been acknowledged and serviced Active low Inactive state is programmable in register GL CR1 RST D8 I Reset An act...

Page 18: ...SDA 0 SDA 1 SDA 2 SDA 3 SDA 4 SDA 5 SDA 6 SDA 7 SDA 8 SDA 9 SDA 10 SDA 11 N9 N10 L11 K11 L7 L8 L9 L5 M5 M7 M8 N8 O SDRAM Address Bus 0 to 11 The 12 pins of the SDRAM address bus output the row addres...

Page 19: ...t enables SDRAM access QUEUE STATUS QOVF C7 O Queue Overflow This pin goes high when the transmit or receive queue has overflowed This pin will go low when the high watermark is reached again JTAG INT...

Page 20: ...VDD3 3 Connect to 3 3V Power Supply VDD1 8 D3 D2 E3 F4 J4 K4 L3 F10 E11 E12 D12 M13 L12 I VDD1 8 Connect to 1 8V Power Supply VSS A9 A12 B10 C10 D1 D5 E7 E8 F6 F8 F12 F13 J5 J6 J11 J7 J8 J9 J10 K3 K5...

Page 21: ...INT VDD1 8 NC VSS JTMS VSS NC VDD1 8 SDATA 29 VSS VSS G RSYNC RCLKI TSYNC SDMASK 1 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 SDATA 30 SDATA 28 SDCLKI H RSER VDD3 SDATA 10 SCAS VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 SDATA...

Page 22: ...om the Packet interface to the WAN interface The Transmit Queue stores data to be sent from the WAN interface to the Packet interface The external SDRAM can accommodate up to 8192 frames with a maximu...

Page 23: ...nected to the microprocessor interrupt input The register map is shown in Table 9 1 8 1 1 Read Write Data Strobe Modes The processor interface can operate in either read write strobe mode or data stro...

Page 24: ...clocks provided by an Ethernet PHY In the DCE mode these are output pins and will output an internally generated clock to the Ethernet PHY The output clocks are generated by internal division of REF_C...

Page 25: ...er Dev Div by 2 4 12 Output Clocks 25 50 Mhz 100 Mhz Oscillator SYSCLKI SDCLKO Buffer Div by 1 2 4 8 10 Output clocks 50 25 Mhz 2 5 Mhz 50 or 25 Mhz Oscillator TX_CLK1 RX_CLK1 TCLKI1 RCLKI1 REF_CLKO 5...

Page 26: ...O pin is automatically determined by the DS33Z41 based on the state of the RMIIMIIS pin The REF_CLKO function can be turned off with the GL CR1 RFOO bit Note that in DCE and RMII operating modes the R...

Page 27: ...STPD RST bit The Serial Interface includes the HDLC encoder decoder X86 encoder and decoder and the corresponding serial port The Serial Interface reset bit LI RSTPD RST stays set after a one is writt...

Page 28: ...TEP 8 Configure the Ethernet Port register space as needed STEP 9 Configure the Ethernet MAC indirect registers as needed STEP 10 Configure the external Ethernet PHYs through the MDIO interface STEP 1...

Page 29: ...us to the next level of interrupt logic they must be enabled by placing a 1 in the associated bit location of the correct Interrupt Enable Register The Interrupt enable registers are LI TPPSRIE LI RPP...

Page 30: ...RX86S LI RX86LSIE Reserved 7 Reserved 6 Reserved 5 Reserved 4 Transmit Queue FIFO Overflowed 3 Transmit Queue Overflow 2 Transmit Queue for Connection Exceeded Low Threshold 1 Transmit Queue for Conn...

Page 31: ...l four T1 E1 links etc Channel 1 is never used for data In T1 mode channels 5 9 13 17 21 25 29 are also not used for data Bytes for all unused timeslots will be replaced with FFh All 4 TDM links must...

Page 32: ...31 L3 31 L4 31 L1 32 L2 32 L3 32 L4 32 s01 s01 s01 s01 xxxx xxxx xxxx xxxx Sequence 02 L1 03 L2 03 L3 03 L4 03 L1 04 L2 04 L3 04 L4 04 L1 31 L2 31 L3 31 L4 31 L1 32 L2 32 L3 32 L4 32 s02 s02 s02 s02...

Page 33: ...links are synchronized Resetting the queue pointers in GL C1QPR Monitoring the TOOFLS1 4 status from GL IMXOOFLS to restart handshaking procedure if needed The host microprocessor is also responsible...

Page 34: ...d receive commands specific to that link The microprocessor can disable links that are not to be aggregated Figure 8 5 Command Structure for IMUX Function 1 Command Even Parity M S B L S B Table 8 3 C...

Page 35: ...gister for the IMXSS register IMUX Interrupt Mask Register GL IMXSIE Interrupt enable bits for Sync Latched Status bits Differential Delay Register GL IMXDFD Provides the largest differential delay va...

Page 36: ...one indicating a single frame slip it is considered a sequence error Two consecutive frames with sequence errors result in an OOF state being declared The OOF state is used to set OOF Latched bits in...

Page 37: ...onnections are not supported When the user changes the queue sizes the connection must be torn down and re established When a connection is disconnected all transmit and receive queues associated with...

Page 38: ...ial Interface Note that once connection is set up then the queues and thresholds can be setup for that connection AR TQSC1 Size for the Transmit Queue in Number of 32 2K packets AR RQSC1 Size for the...

Page 39: ...ote that the user does not have control over SU MACFCR FCE and FCB bits if ATFLOW is set The mechanism of sending pause or jam is dependent only on the receive queue high threshold Manual flow control...

Page 40: ...frame is received Pause is sent every time a frame is received in the high threshold state Pause control will only take care of temporary congestion Pause control does not take care of systems where...

Page 41: ...is being received during the watermark crossing but will wait to jam the next frame after the SU RQHT bit is set If the queue remains above the high threshold received frames will continue to be jamm...

Page 42: ...ed Each Ethernet frame sent or received generates status bits SU TFSH and SU TFSL and SU RFSB0 to SU RFSB3 These are real time status registers and will change as each frame is sent or received Hence...

Page 43: ...e registers provide the real time status for the received frame Only apply to the last frame received SU RFRC This register provides settings for reception or rejection of frame based on errors detect...

Page 44: ...nfigured as DTE Connected to an Ethernet PHY in MII Mode MAC RXD 3 0 RXD 3 0 RX_CLK RX_CLK RX_ERR RX_ERR RX_CRS RX_CRS COL_DET COL_DET Ethernet Phy TX_EN TX_EN MDC MDIO TXD 3 0 TXD 3 0 TX_CLK DS33Z41...

Page 45: ...Figure 8 9 DS33Z41 Configured as a DCE in MII Mode MAC TXD 3 0 RXD 3 0 TX_CLK RX_CLK TX_ERR RX_ERR TX_EN RX_CRS COL_DET COL_DET DTE DCE TX_EN RXDV MDC MDIO TXD 3 0 RXD 3 0 TX_CLK DS33Z41 WAN MAC RX_C...

Page 46: ...egisters ADDRESS REGISTER DESCRIPTION 0000h 0003h SU MACCR MAC Control Register This register is used for programming full duplex half duplex promiscuous mode and back off limit for half duplex The tr...

Page 47: ...2 RMII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high RMII interface operates synchronously from the external 50MHz reference REF_CLK Only 7...

Page 48: ...of BERT patterns The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment The following restrict...

Page 49: ...n PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern The receive pattern generator is synchronized by loading 32 data stream bits into the receive pat...

Page 50: ...s a 32 bit shift register that shifts data from the least significant bit LSB or bit 1 to the most significant bit MSB or bit 32 The input to bit 1 is the feedback For a PRBS pattern generating polyno...

Page 51: ...erformance monitoring update signal PMU During the counter register update process the performance monitoring status signal PMS is deasserted The counter register update process consists of loading th...

Page 52: ...pted in each errored packet The FCS bit corrupted is changed from errored packet to errored packet Error insertion can be controlled by a register or by the manual error insertion input LI TMEI TMEI T...

Page 53: ...hen the inter frame fill is flags the flags may have a shared zero 011111101111110 If there is less than 16 bits between two flags the data is discarded If packet processing is disabled inter frame fi...

Page 54: ...nd the LSB in RFD 0 or 8 16 or 24 of the receive FIFO data RFD 7 0 or 15 8 23 16 or 31 24 If bit reordering is enabled the incoming 8 bit data stream DT 1 8 is output to the Receive FIFO with the MSB...

Page 55: ...NET SDH network The DS33Z41 expects a byte synchronization signal to provide the byte boundary for the X 86 receiver This is provided by the RSYNC pin The functional timing is shown in Figure 11 7 The...

Page 56: ...e serial stream if configured for X 86 mode in the register LI TX86E The DS33Z41 provides the following functions Control Registers for Address SAPI Destination Address Source Address 32 bit FCS enabl...

Page 57: ...7e or dd is detected For the transmitter if X 86 is enabled the sequence of processing is as follows Construct frame including start flag SAPI Control and MAC frame Calculate FCS Perform transparency...

Page 58: ...e sent to the Serial Interface the interface will request the data if there is a positive credit balance If the credit balance is negative transmit interface does not request data New credit balance i...

Page 59: ...er Dev Div by 2 4 12 Output Clocks 25 50 Mhz 100 Mhz Oscillator SYSCLKI SDCLKO Buffer Dev Div by 1 2 4 8 10 Output clocks 50 25 Mhz 2 5 Mhz 50 or 25 Mhz Oscillator TX_CLK1 RX_CLK1 TCLKI1 RCLKI1 REF_CL...

Page 60: ...t The registers associated with the MAC must be configured through indirect register write read access due to the architecture of the device When writing to a register input values for unused bits and...

Page 61: ...IBIE IMUXIE BIE 00Dh GL IBIS IIS BIS 00Eh GL CON1 LINE1 0 012h GL C1QPR C1MRPRR C1HWPRR C1MHPR C1HRPR 016h GL IMXCN T1E1 RXE SENDE L4 L3 L2 L1 017h GL IMXC IMUXC7 IMUXC6 IMUXC5 IMUXC4 IMUXC3 IMUXC2 IM...

Page 62: ...5h BSPB1R BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8 086h BSPB2R BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16 087h BSPB3R BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24 088h TEICR TIER2 TIER1 T...

Page 63: ...2 TPC21 TPC20 TPC19 TPC18 TPC17 TPC16 0CFh Reserved 0D0h LI TBCR0 TBC7 TBC6 TBC5 TBC4 TBC3 TBC2 TBC1 TBC0 0D1h LI TBCR1 TBC15 TBC14 TBC13 TBC12 TBC11 TBC10 TBC9 TBC8 0D2h LI TBCR2 TBC23 TBC22 TBC21 TB...

Page 64: ...18 RAPC17 RAPC16 113h Reserved 114h LI RSPCB0 RSPC7 RSPC6 RSPC5 RSPC4 RSPC3 RSPC2 RSPC1 RSPC0 115h LI RSPCB1 RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 116h LI RSPCB2 RSPC23 RSPC22 RSPC21 R...

Page 65: ...MACD31 MACD30 MACD29 MACD28 MACD27 MACD26 MACD25 MACD24 14Ah SU MACAWL MACAW 7 MACAW 6 MACAW 5 MACAW4 MACAW3 MACAW2 MACAW1 MACAW0 14Bh SU MACAWH MACAW 15 MACAW 14 MACAW 13 MACAW12 MACAW11 MACAW10 MACA...

Page 66: ...7 0 PADR07 PADR06 PADR05 PADR04 PADR03 PADR02 PADR01 PADR00 000Ch Reserved 000Dh Reserved 000Eh Reserved 000Fh Reserved 0010h Reserved 0011h Reserved 0012h Reserved 0013h Reserved 0014h SU MACMIIA 31...

Page 67: ...C23 TXBYTEC22 TXBYTEC21 TXBYTEC20 TXBYTEC19 TXBYTEC18 TXBYTEC17 TXBYTEC16 30Ah 15 8 TXBYTEC15 TXBYTEC14 TXBYTEC13 TXBYTEC12 TXBYTEC11 TXBYTEC10 TXBYTEC9 TXBYTEC8 30Bh 7 0 TXBYTEC7 TXBYTEC6 TXBYTEC5 TX...

Page 68: ...e contains a RMII interface Bit 4 ID04 If this bit is set the device contains a MII interface Bit 3 ID03 If this bit is set the device contains an Ethernet PHY Bits 2 to 0 ID03 to ID00 A three bit cou...

Page 69: ...the internal data path and status and control registers except this RST bit on all ports are reset to their default state This bit must be set high for a minimum of 100ns 0 Normal operation 1 Reset an...

Page 70: ...ead Bit 0 Transmit Serial Interface Clock Activity Latched Status 1 TLCALS1 This bit is set to 1 if the transmit clock for Serial Interface 1 has activity This bit is cleared upon read Register Name G...

Page 71: ...ing event Serial Interface interrupts consist of HDLC interrupts and X 86 interrupts Bit 0 Serial Interface 1 Rx Interrupt Status LIN1RIS This bit is set if Serial Interface 1 Receive has an enabled i...

Page 72: ...ue crossing thresholds and queue overflows Bit 0 Receive Queue 1 Interrupt Status RQ1IS If this bit is set to 1 the Receive Queue 1 has interrupt status event Receive queue events are transmit queue c...

Page 73: ...t 7 6 5 4 3 2 1 0 Name C1MRPRR C1HWPRR C1MHPR C1HRPR Default 0 0 0 0 0 0 0 0 Bit 3 MAC Read Pointer Reset C1MRPR Setting this bit to 1 resets the receive queue read pointer for connection 1 This queue...

Page 74: ...on If this bit is equal to 0 the link does not participate Bit 1 Link 2 L2 If this bit is set to 1 link number two is participating in the communication If this bit is equal to 0 the link does not par...

Page 75: ...local end is in sync for the 3rd portion of the 8 192Mbps link The command states that the local end is in sync Bit 1 IMUX Receive Sync 2 IRSYNC2 If this bit is set to 1 the local end is in sync for...

Page 76: ...bit for IRSYNC2 Bit 0 IMUX Receive Sync Latched Status 1 IRSYNCLS1 This is a latched status bit for IRSYNC1 Register Name GL IMXDFD Register Description Inverse MUX Diff Delay Register Address 1Bh Bi...

Page 77: ...interrupt on TOOFLS3 Bit 5 IMUX Transmit OOF Interrupt Enable 2 TOOFIE2 Setting this bit to 1 enables an interrupt on TOOFLS2 Bit 4 IMUX Transmit OOF Interrupt Enable 1 TOOFIE1 Setting this bit to 1 e...

Page 78: ...bit for Receiver OOF this bit is set if the receiver end is out of frame Bit 1 IMUX Receive Sync Latched Status 2 ROOFLS2 This is a latched bit for Receiver OOF this bit is set if the receiver end is...

Page 79: ...lue of this register the user must toggle the GL SDMODEWS SDMW bit to write the new values to the SDRAM Register Name GL SDMODE2 Register Description Global SDRAM Mode Register 2 Register Address 3Bh...

Page 80: ...0 1 1 0 Bits 7 to 0 SDRAM Refresh Time Control SREFT7 to SREFT0 These 8 bits are used to control the SDRAM refresh frequency The refresh rate will be equal to this register value x 8 x 100MHz Note Th...

Page 81: ...ta arriving from the MAC to be sent to the WAN The Queue address size is defined in increments of 32 x 2048 bytes The queue size is AR RQSC1 multiplied by 32 to determine the number of 2048 byte packe...

Page 82: ...g data stream is not altered When 1 the receive incoming data stream is inverted Bit 3 Manual Pattern Resynchronization MPR A zero to one transition of this bit will cause the receive pattern generato...

Page 83: ...all zero Bit 5 Pattern Type Select PTS When 0 the pattern is a PRBS pattern When 1 the pattern is a repetitive pattern Bits 4 to 0 Pattern Length Feedback PLF4 to PLF0 These five bits control the leng...

Page 84: ...Byte 2 Register Register Address 86h Bit 7 6 5 4 3 2 1 0 Name BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 BERT Pattern BSP23 to BSP16 8 bits of 32 bits Register...

Page 85: ...Insert TSEI This bit causes a bit error to be inserted in the transmit data stream if and single bit error insertion is enabled A 0 to 1 transition causes a single bit error to be inserted For a seco...

Page 86: ...state Register Name BSRIE Register Description BERT Status Register Interrupt Enable Register Address 90h Bit 7 6 5 4 3 2 1 0 Name PMSIE BEIE BECIE OOSIE Default 0 0 0 0 0 0 0 0 Bit 3 Performance Moni...

Page 87: ...ription below Register Name RBECR2 Register Description Receive Bit Error Count Byte 2 Register Register Address 96h Bit 7 6 5 4 3 2 1 0 Name BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16 Default 0...

Page 88: ...BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Bit Count BC23 to BC16 Eight bits of a 32 bit value Register description below Register Name RBCB3 Register Description Rece...

Page 89: ...ing Once cleared a latched bit will not be set again until the associated event occurs again Reserved configuration bits and registers should be written to zero 9 5 1 Serial Interface Transmit and Com...

Page 90: ...2 bit FCS processing is enabled Bit 3 Transmit Bit Synchronous Inter Frame Fill Value TIFV When 0 inter frame fill is done with the flag sequence 7Eh When 1 inter frame fill is done with all ones This...

Page 91: ...of TIFG 7 0 plus 1 Note If inter frame fill is set to all ones a TFIG value of 2 or 3 will result in a flag two bytes of ones and an additional flag between packets Register Name LI TEPLC Register De...

Page 92: ...y which has a maximum value of 6 If TPER 3 0 has a value of 0h errored packet insertion is disabled If TPER 6 4 has a value of 6xh or 7xh the errored packet rate is x 106 A TPER 6 0 value of 01h resu...

Page 93: ...initiated Register Name LI TPPSRL Register Description Transmit Packet Processor Status Register Latched Register Address 0C9h Bit 7 6 5 4 3 2 1 0 Name TEPFL Default Bit 0 Transmit Errored Packet Ins...

Page 94: ...Count Byte 1 Register Address 0CDh Bit 7 6 5 4 3 2 1 0 Name TPC15 TPC14 TPC13 TPC12 TPC11 TPC10 TPC9 TPC8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Transmit Packet Count TPC15 to TPC8 Eight bits of 24 bit v...

Page 95: ...cription Transmit Byte Count Byte 2 Register Address 0D2h Bit 7 6 5 4 3 2 1 0 Name TBC23 TBC22 TBC21 TBC20 TBC19 TBC18 TBC17 TBC16 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Transmit Byte Count TBC23 TBC16 E...

Page 96: ...unters to be updated A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data and the counters reset 0 or 1 This update updates performance monitoring counter...

Page 97: ...9h Bit 7 6 5 4 3 2 1 0 Name X86TRA7 X86TRA6 X86TRA5 X86TRA4 X86TRA3 X86TRA2 X86TRA1 X86TRA0 Default 0 0 0 0 0 1 0 0 Bits 7 to 0 X86 Transmit Receive Address X86TRA7 to X86TRA0 This is the address fiel...

Page 98: ...R1 CIR0 Default 0 0 0 0 0 0 0 1 Bit 7 Committed Information Rate Enable CIRE Set this bit to 1 to enable the Committed Information Rate Controller feature Bits 6 to 0 Committed Information Rate CIR6 t...

Page 99: ...Bit 3 Receive FCS Extraction Disable RFED When 0 the FCS bytes are discarded When 1 the FCS bytes are passed on This bit is ignored when FCS processing is disabled In X 86 mode FCS bytes are discarde...

Page 100: ...g data is to be broken into The maximum packet size allowable is 2016 bytes plus the FCS bytes Any values programmed that are greater than 2016 FCS will have the same effect as 2016 FCS value In X 86...

Page 101: ...n a packet with a non integer number of bytes is detected Bit 4 Receive Small Packet Detected Latched RSPDL This bit is set when a packet smaller than the minimum packet size is detected Bit 3 Receive...

Page 102: ...terrupt enabled Bit 4 Receive Small Packet Detected Interrupt Enable RSPDIE This bit enables an interrupt if the RSPDL bit in the LI RPPSRL register is set 0 interrupt disabled 1 interrupt enabled Bit...

Page 103: ...15 RPC14 RPC13 RPC12 RPC11 RPC10 RPC09 RPC08 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Receive Packet Count RPC15 to RPC8 Eight bits of a 24 bit value Register description below Register Name LI RPCB2 Regis...

Page 104: ...dress 10Dh Bit 7 6 5 4 3 2 1 0 Name RFPC15 RFPC14 RFPC13 RFPC12 RFPC11 RFPC10 RFPC9 RFPC8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Receive FCS Errored Packet Count RFPC15 to RFPC8 Eight bits of a 24 bit va...

Page 105: ...3 2 1 0 Name RAPC15 RAPC14 RAPC13 RAPC12 RAPC11 RAPC10 RAPC9 RAPC8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Receive Aborted Packet Count RAPC15 to RAPC8 Eight bits of a 24 bit value Register description b...

Page 106: ...RSPC15 RSPC14 RSPC13 RSPC12 RSPC11 RSPC10 RSPC9 RSPC8 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 Receive Size Violation Packet Count RSPC15 to RSPC8 Eight bits of a 24 bit value Register description below Re...

Page 107: ...ter description below Register Name LI RBC2 Register Description Receive Byte Count 2 Register Register Address 11Ah Bit 7 6 5 4 3 2 1 0 Name RBC23 RBC22 RBC21 RBC20 RBC19 RBC18 RBC17 RBC16 Default 0...

Page 108: ...ster description below Register Name LI RAC2 Register Description Receive Aborted Byte Count 2 Register Register Address 11Eh Bit 7 6 5 4 3 2 1 0 Name REBC23 REBC22 REBC21 REBC20 REBC19 REBC18 REBC17...

Page 109: ...RPMUUS This bit is set when the Transmit PMU Update is completed This bit is cleared when RPMUU is set to 0 Register Name LI RX86S Register Description Receive X 86 Latched Status Register Register A...

Page 110: ...it is set to 1 LI RX86S CNE will generate an interrupt Bit 0 Address Not Equal to LI TRX86A Interrupt Enable ANE4IM If this bit is set to 1 LI RX86S ANE will generate an interrupt Register Name LI TQL...

Page 111: ...it is set the watermark interrupt is enabled for TQOVFLS Bit 1 Transmit Queue for Connection High Threshold Interrupt Enable TQHTIE If this bit is set the watermark interrupt is enabled for TQHTS Bit...

Page 112: ...ACRA7 MACRA6 MACRA5 MACRA4 MACRA3 MACRA2 MACRA1 MACRA0 Default 0 0 0 0 0 0 0 0 Bits 7 to 0 MAC Read Address MACRA7 to MACRA0 Low byte of the MAC address Used only for read operations Register Name SU...

Page 113: ...our bytes of data read from the MAC Valid after a read command has been issued and the SU MACRWC MCS bit is zero Register Name SU MACRD3 Register Description MAC Read Data Byte 3 Register Address 145h...

Page 114: ...MAC Write Data 2 MACWD23 to MACWD16 One of four bytes of data to be written to the MAC Data has been written after a write command has been issued and the SU MACRWC MCS bit is zero Register Name SU MA...

Page 115: ...Bit 1 MAC Command RW MCRW If this bit is written to 1 a read is performed from the MAC If this bit is written to 0 a write operation is performed Address information for write operations must be locat...

Page 116: ...this includes the 4 bytes of CRC Bit 2 H10S This bit controls the 10 100 selection for RMII and DCE Mode When in RMII mode setting this bit to 1 will cause the MAC will operate at 100Mbps and setting...

Page 117: ...diately instead of being deferred If this bit is set to 0 the frame is deferred if CRS is asserted and sent when the CRS is unasserted indicating the media is idle Bit 1 Transmit Packet HB Fail Contro...

Page 118: ...Valid only in half duplex operation Bit 2 No Carrier NOC When this bit is set to 1 a frame was aborted because no carrier was found for transmission Bit 0 Frame Abort FABORT When this bit is set to 1...

Page 119: ...upper bits of the length in bytes of the received frame with FCS and Padding If Automatic Pad Stripping is enabled this value is the length of the received packet without PCS or Pad bytes Register Na...

Page 120: ...Frame MCF This bit is set to 1 if the current frame is a multicast frame Bit 2 Unsupported Control Frame UF This bit is set to 1 if the frame received is a control frame with an opcode that is not sup...

Page 121: ...behavior and should be avoided Register Name SU RQLT Register Description Receive Queue Low Threshold Watermark Register Address 15Ah Bit 7 6 5 4 3 2 1 0 Name RQLT7 RQLT6 RQLT5 RQLT4 RQLT3 RQLT2 RQLT...

Page 122: ...RLS Register Description Queue Cross Threshold Latched Status Register Address 15Dh Bit 7 6 5 4 3 2 1 0 Name RFOVFLS RQOVFLS RQHTLS RQLTLS Default Bit 3 Receive FIFO Overflow latched Status RFOVFLS Th...

Page 123: ...actual number of bytes received are allowed When equal to zero only frames with matching length fields and actual bytes received will be allowed Bit 3 CRC Error Reject CRCERR When set to 1 frames rec...

Page 124: ...C Reserved TE RE Reserved Reserved Default 0 0 0 0 0 0 0 0 Bit 28 Heartbeat Disable HDB When set to 1 the heartbeat SQE function is disabled This bit should be set to 1 when operating in MII mode Bit...

Page 125: ...ollided packets Default operation limits the maximum delay for retransmission to a countdown of 10 bits from a random number generator The user can reduce the maximum number of counter bits as describ...

Page 126: ...1 1 Bits 31 to 00 PADR47 to PADR32 These 32 bits should be initialized with the upper 4 bytes of the Physical Address for this MAC device Register Name SU MACAL Register Description MAC Address Low R...

Page 127: ...eserved Reserved Reserved Reserved MIIW MIIB Default 1 1 0 0 0 0 0 0 Bits 15 to 11 PHY Address PHYA4 to PHYA0 These 5 bits select one of the 32 available PHY address locations to access through the PH...

Page 128: ...20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 001Ah Bit 15 14 13 12 11 10 09 08 Name MIID15 MIID14 MIID13 MIID12 MIID11 MIID10 MII...

Page 129: ...d Reserved Reserved FCE FCB Default 0 0 0 0 0 0 1 0 Bits 31 to 16 Pause Time PT15 to PT00 These bits are used for the Pause Time Field in transmitted Pause Frames This value is the number of time slot...

Page 130: ...eserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0102h Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved MXFRM10 MXFRM9 MXFRM8 MXFRM7 MXFRM6 MXFRM5 Default 0 0 1 0 1 1 1 1 0103h Bit 07 06 0...

Page 131: ...21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 010Eh Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved Reserved Reser...

Page 132: ...21 20 19 18 17 16 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 0112h Bit 15 14 13 12 11 10 09 08 Name Reserved Reserved Reserved Reserved Reser...

Page 133: ...0 0 0203h Bit 07 06 05 04 03 02 01 00 Name RXFRMC7 RXFRMC6 RXFRMC5 RXFRMC4 RXFRMC3 RXFRMC2 RXFRMC1 RXFRMC0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 All Frames Received Counter RXFRMC31 to RXFRMC0 32 bit v...

Page 134: ...h Bit 07 06 05 04 03 02 01 00 Name RXFRMOK7 RXFRMOK6 RXFRMOK5 RXFRMOK4 RXFRMOK3 RXFRMOK2 RXFRMOK1 RXFRMOK0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 Frames Received OK Counter RXFRMOK31 to RXFRMOK0 32 bit...

Page 135: ...0303h Bit 07 06 05 04 03 02 01 00 Name TXFRMC7 TXFRMC6 TXFRMC5 TXFRMC4 TXFRMC3 TXFRMC2 TXFRMC1 TXFRMC0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 All Frames Transmitted Counter TXFRMC31 to TXFRMC0 32 bit v...

Page 136: ...0 0 0 0 0 030Bh Bit 07 06 05 04 03 02 01 00 Name TXBYTEC7 TXBYTEC6 TXBYTEC5 TXBYTEC4 TXBYTEC3 TXBYTEC2 TXBYTEC1 TXBYTEC0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 All Bytes Transmitted Counter TXBYTEC31 t...

Page 137: ...0 030Fh Bit 07 06 05 04 03 02 01 00 Name TXBYTEOK7 TXBYTEOK6 TXBYTEOK5 TXBYTEOK4 TXBYTEOK3 TXBYTEOK2 TXBYTEOK1 TXBYTEOK0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 Bytes Transmitted OK Counter TXBYTEOK31 to...

Page 138: ...03 02 01 00 Name TXFRMU7 TXFRMU6 TXFRMU5 TXFRMU4 TXFRMU3 TXFRMU2 TXFRMU1 TXFRMU0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 Frames Aborted Due to FIFO Under Run Counter TXFRMU31 to TXFRMU0 32 bit value indi...

Page 139: ...0 0 033Bh Bit 07 06 05 04 03 02 01 00 Name TXFRMBD7 TXFRMBD6 TXFRMBD5 TXFRMBD4 TXFRMBD3 TXFRMBD2 TXFRMBD1 TXFRMBD0 Default 0 0 0 0 0 0 0 0 Bits 31 to 0 All Frames Aborted Counter TXFRMBD31 to TXFRMBD0...

Page 140: ...n Half Duplex DTE Mode the DS33Z41 supports CRS and COL signals CRS is active when the PHY detects transmit or receive activity If there is a collision as indicated by the COL input the DS33Z41 will r...

Page 141: ...de Figure 10 3 MII Receive Functional Timing RXD 3 0 RX_CLK P R E A E M B L E F C S In RMII Mode TX_EN is high with the first bit of the preamble The TXD 1 0 is synchronous with the 50MHz REF_CLK For...

Page 142: ...d below are not production tested Table 11 1 Recommended DC Operating Conditions VDD3 3 3 3V 5 VDD1 8 1 8 5 Tj 40 C to 85 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 1 VIH 2 0 3 465 V Logic...

Page 143: ...al Characteristics Table 11 3 Thermal Characteristics PARAMETER MIN TYP MAX NOTES Ambient Temperature 40 C 85 C 1 Junction Temperature 125 C Theta JA JA in Still Air for 169 Pin 14mm CSBGA 52 7 C W 2...

Page 144: ...I Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS TX_CLK Period t1 400 40 ns TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 260 14 26 ns TX_CLK to TXD TX_EN Delay...

Page 145: ...SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK Period t5 400 40 ns RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns RXD RX_DV to RX_CLK Setup Time t8 5 5 ns RX_CLK to RXD RX_DV H...

Page 146: ...100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CLK Frequency 50MHz 50ppm 50MHz 50ppm REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns REF_CLK t...

Page 147: ...TYP MAX UNITS REF_CLK Frequence 50MHz 50ppm 50MHz 50ppm MHz REF_CLK Period t1 20 20 ns REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns RXD CRS_DV to REF_CLK Setup Time t8 5 5 ns RE...

Page 148: ...RAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1 67 MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time...

Page 149: ...N Interface PARAMETER SYMBOL MIN TYP MAX UNITS TCLKI Frequency 52 MHz TCLKI Period t1 19 2 ns TCLKI Low Time t2 8 ns TCLKI High Time t3 8 ns TCLKI to TSER Output Delay t4 3 10 ns TSYNC Setup Time t5 3...

Page 150: ...ce PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI Frequency 52 MHz RCLKI Period t1 19 2 ns RCLKI Low Time t2 8 ns RCLKI High Time t3 8 ns RSER Setup Time t4 7 ns RSYNC Setup Time t4 7 ns RSER Hold Time t5 2...

Page 151: ...SDRAM t5 3 ns SDCLKO to SDATA Drive Off Write to SDRAM t6 4 ns SDATA to SDCLKO Setup Time Read from SDRAM t7 2 ns SDCLKO to SDATA Hold Time Read from SDRAM t8 2 ns SDCLKO to SRAS SCAS SWE SDCS Active...

Page 152: ...ad IMUX Ethernet Mapper 152 of 167 Figure 11 8 SDRAM Interface Timing SDCLKO output SDATA output t1 SDATA input SRAS SCAS SWE SDCS output t2 t3 t5 t6 t7 t8 t10 t9 SDA SBA output SDMASK output t4 t12 t...

Page 153: ...ming Note 1 8 192MHz bus configuration Note 2 Data on unused channels must be filled with all ones RSER LSB RCLKI RSYNC LINK 4 CHANNEL 32 MSB LSB LINK 1 CHANNEL 1 MSB LSB LINK 2 CHANNEL 1 RSYNC RSER L...

Page 154: ...DS33Z41 Quad IMUX Ethernet Mapper 154 of 167 Figure 11 10 Transmit IBO Channel Interleave Mode Timing Note 1 8 192MHz bus configuration Note 2 Unused channels filled with FFh...

Page 155: ...for CS Active to either RD or WR Active t2 0 ns Delay Time from Either RD or DS Active to DATA 7 0 Valid t3 75 ns Hold Time from Either RD or WR Inactive to CS Inactive t4 0 ns Hold Time from CS or R...

Page 156: ...of 167 Figure 11 11 Intel Bus Read Timing MODEC 00 t2 t3 Address Valid Data Valid t4 t9 t5 t10 ADDR 12 0 DATA 7 0 CS RD WR t1 Figure 11 12 Intel Bus Write Timing MODEC 00 t2 t6 Address Valid t4 t9 t10...

Page 157: ...167 Figure 11 13 Motorola Bus Read Timing MODEC 01 t2 t3 Address Valid Data Valid t4 t9 t5 t10 ADDR 12 0 DATA 7 0 CS DS RW t1 Figure 11 14 Motorola Bus Write Timing MODEC 01 t2 t6 Address Valid t4 t9...

Page 158: ...TS JTCLK Clock Period t1 1000 ns JTCLK Clock High Low Time t2 t3 Note 1 50 500 ns JTCLK to JTDI JTMS Setup Time t4 2 ns JTCLK to JTDI JTMS Hold Time t5 2 ns JTCLK to JTDO Delay t6 2 50 ns JTCLK to JTD...

Page 159: ...Instruction Register Bypass Register Boundary Scan Register Device Identification Register The Test Access Port has the necessary interface pinsL JTRST JTCLK JTMS JTDI and JTDO See the pin description...

Page 160: ...selected by the current instruction If the instruction does not call for a parallel load or the selected register does not allow parallel loads the test register will remain at its current value On th...

Page 161: ...ut The parallel register as well as all test registers remains at their previous states A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1 IR state A rising edge on JTCLK with...

Page 162: ...e towards the serial output at JTDO A rising edge on JTCLK in the Exit1 IR state or the Exit2 IR state with JTMS HIGH will move the controller to the Update IR state The falling edge of that same JTCL...

Page 163: ...following actions occur Once enabled via the Update IR state the parallel outputs of all digital output pins are driven The boundary scan register is connected between JTDI and JTDO The Capture DR wi...

Page 164: ...unction with the IDCODE instruction and the Test Logic Reset state of the TAP controller 12 4 1 Boundary Scan Register This register contains both a shift register path and a latched parallel output f...

Page 165: ...X01 pattern Shifting the TDI pin to the TDO pin through the bypass shift register An asynchronous reset occurs while shifting Figure 12 3 JTAG Functional Timing JTCLK JTRST JTMS JTDI JTDO STATE Reset...

Page 166: ...ACKAGE INFORMATION The package drawing s in this data sheet may not reflect the most current specifications The package number provided for each package is a link to the latest package outline informa...

Page 167: ...C Corrected default value listed in the SU RMFSRL register definition Added GL SDMODE1 GL SDMODE2 GL SDMODEWS and GL SDRFTC register definitions Added GL SDMODE1 GL SDMODE2 GL SDMODEWS and GL SDRFTC r...

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