DS33Z41 Quad IMUX Ethernet Mapper
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1 DESCRIPTION
The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86 (LAPS) Mapper,
SDRAM interface, control ports, and Bit Error Rate Tester (BERT). The packet interface consists of an Ethernet
interface using several physical layer protocols. The Ethernet interface can be configured for 10Mbps or 100Mbps
service. The DS33Z41 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) to be transmitted over the WAN
interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets
over the Ethernet port. The WAN physical interface is based on the Dallas Semiconductor Interleaved Bus
Operation (IBO), running at 8.192Mbps. The IBO interface can be configured to allow up to four bonded T1 or E1
data streams. The IBO interface provides for seamless connection to the Dallas Semiconductor/Maxim multi-port
T1/E1/J1 Framers and Single-Chip Transceivers (SCTs). See
Application Note 3411: DS33Z11—Ethernet LAN to
Unframed T1/E1 WAN Bridge
for an example of a complete LAN to WAN solution.
The DS33Z41 is controlled through an 8-bit microcontroller port. The DS33Z41 has a 100MHz SDRAM controller
and interfaces to a 32-bit wide 128Mb SDRAM. The SDRAM is used to buffer the data from the Ethernet and
WAN ports for transport. The external SDRAM can accommodate up to 8192 frames with a maximum frame size
of 2016 bytes. The DS33Z41 operates with a 1.8V core supply and 3.3V I/O supply.