DS33Z41 Quad IMUX Ethernet Mapper
138 of 167
Register Name:
SU.TXFRMUNDR
Register Description:
MAC Transmit Frame Under Run Counter
Register Address:
0334h (indirect)
0334h:
Bit
# 31 30 29 28 27 26 25 24
Name
TXFRMU31 TXFRMU30 TXFRMU29 TXFRMU28 TXFRMU27 TXFRMU26 TXFRMU25 TXFRMU24
Default
0 0 0 0 0 0 0 0
0335h:
Bit
# 23 22 21 20 19 18 17 16
Name
TXFRMU23 TXFRMU22 TXFRMU21 TXFRMU20 TXFRMU19 TXFRMU18 TXFRMU17 TXFRMU16
Default
0 0 0 0 0 0 0 0
0336h:
Bit
# 15 14 13 12 11 10 09 08
Name
TXFRMU15 TXFRMU14 TXFRMU13 TXFRMU12 TXFRMU11 TXFRMU10 TXFRMU9 TXFRMU8
Default
0 0 0 0 0 0 0 0
0337h:
Bit
# 07 06 05 04 03 02 01 00
Name
TXFRMU7 TXFRMU6 TXFRMU5
TXFRMU4 TXFRMU3 TXFRMU2 TXFRMU1 TXFRMU0
Default
0 0 0 0 0 0 0 0
Bits 31 to 0: Frames Aborted Due to FIFO Under Run Counter (TXFRMU31 to TXFRMU0).
32-bit value
indicating the number of frames aborted due to FIFO under run. Each time a frame is aborted due to FIFO under
run, this counter is incremented by 1. This counter resets only upon device reset, does not saturate, and rolls over
to zero upon reaching the maximum value. The user should ensure that the measurement period is less than the
minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. The user
should store the value from the beginning of the measurement period for later calculations, and take into account
the possibility of a rollover occurring.