DS33Z41 Quad IMUX Ethernet Mapper
151 of 167
11.7 SDRAM Timing
Table 11-12. SDRAM Interface Timing
100MHz
PARAMETER SYMBOL
MIN TYP MAX
UNITS
SDCLKO Period
t1
9.7
10
10.3
ns
SDCLKO Duty Cycle
t2
4
6
ns
SDCLKO to SDATA Valid
Write to SDRAM
t3 7
ns
SDCLKO to SDATA Drive On
Write to SDRAM
t4 4 ns
SDCLKO to SDATA Invalid
Write to SDRAM
t5 3 ns
SDCLKO to SDATA Drive Off
Write to SDRAM
t6 4
ns
SDATA to SDCLKO Setup Time
Read from SDRAM
t7 2 ns
SDCLKO to SDATA Hold Time
Read from SDRAM
t8 2
ns
SDCLKO to
SRAS
,
SCAS
,
SWE
,
SDCS
Active
Read or Write to SDRAM
t9 5
ns
SDCLKO TO
SRAS
,
SCAS
,
SWE
,
SDCS
Inactive Read or Write to SDRAM
t10 2
ns
SDCLKO to SDA, SBA Valid
Read or Write to SDRAM
t11 7
ns
SDCLKO TO SDA, SBA Invalid
Read or Write to SDRAM
t12 2
ns
SDCLKO to SDMASK Valid
Read or Write to SDRAM
t13 5
ns
SDCLKO TO SDMASK Invalid
Read or Write to SDRAM
t14 2
ns