DS33Z41 Quad IMUX Ethernet Mapper
15 of 167
NAME PIN
TYPE
FUNCTION
TX_CLK A8
IO
Transmit Clock (MII).
Timing reference for TX_EN and TXD[3:0]. The
TX_CLK frequency is 25MHz for 100Mbps operation and 2.5MHz for
10Mbps operation.
In DTE mode, this is a clock input provided by the PHY. In DCE mode,
this is an output derived from REF_CLK providing 2.5MHz (10Mbps
operation) or 25MHz (100Mbps operation).
TX_EN E10
O
Transmit Enable (MII):
This pin is asserted high when data TXD [3:0] is being provided by the
DS33Z41. The signal is deasserted prior to the first nibble of the next
frame. This signal is synchronous with the rising edge TX_CLK. It is
asserted with the first bit of the preamble.
Transmit Enable (RMII):
When this signal is asserted, the data on TXD [1:0] is valid. This signal
is synchronous to the REF_CLK.
TXD[0]
TXD[1]
TXD[2]
TXD[3]
B9
C9
D9
E9
O
Transmit Data 0 through 3(MII).
TXD [3:0] is presented synchronously
with the rising edge of TX_CLK. TXD [0] is the least significant bit of the
data. When TX_EN is low the data on TXD should be ignored.
Transmit Data 0 through 1(RMII).
Two bits of data TXD [1:0]
presented synchronously with the rising edge of REF_CLK.
RX_CLK A10
IO
Receive Clock (MII).
Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In
DTE mode, this is a clock input provided by the PHY. In DCE mode,
this is an output derived from REF_CLK providing 2.5MHz (10Mbps
operation) or 25MHz (100Mbps operation).
RXD[0]
RXD[1]
RXD[2]
RXD[3]
B11
C11
D11
A11
I
Receive Data 0 through 3(MII).
Four bits of received data, sampled
synchronously with the rising edge of RX_CLK. For every clock cycle,
the PHY transfers 4 bits to the DS33Z41. RXD[0] is the least significant
bit of the data. Data is not considered valid when RX_DV is low.
Receive Data 0 through 1(RMII).
Two bits of received data, sampled
synchronously with REF_CLK with 100Mbps mode. Accepted when
CRS_DV is asserted. When configured for 10Mbps mode, the data is
sampled once every 10 clock periods.
RX_DV D10 I
Receive Data Valid (MII).
This active high signal indicates valid data
from the PHY. The data RXD is ignored if RX_DV is not asserted high.
RX_CRS/
CRS_DV
C8 I
Receive Carrier Sense (MII).
Should be asserted (high) when data
from the PHY (RXD[3:0) is valid. For each clock pulse 4 bits arrive from
the PHY. Bit 0 is the least significant bit. In DCE mode, connect to V
DD
.
Carrier Sense/Receive Data Valid (RMII).
This signal is asserted
(high) when data is valid from the PHY. For each clock pulse 2 bits
arrive from the PHY. In DCE mode, this signal must be grounded.
RX_ERR B12 I
Receive Error (MII).
Asserted by the MAC PHY for one or more
RX_CLK periods indicating that an error has occurred. Active High
indicates Receive code group is invalid. If CRS_DV is low, RX_ERR
has no effect. This is synchronous with RX_CLK. In DCE mode, this
signal must be grounded.
Receive Error (RMII).
Signal is synchronous to REF_CLK.