LSI Symbios SYM53C040, Technical Manual

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Interrupts 2-29
2.10.1.2 Interrupt Mask Register ( 0xFE0D )
Clearing the bits in this register masks the interrupts corresponding to
the bits in the
Interrupt Status (ISR) register.
2.10.1.3 Interrupt Destination Register ( 0xFE0E )
This register provides the ability to route an interrupt to either of the two
external interrupt inputs of the microcontroller core. The bits correspond
to the interrupts in the
Interrupt Status (ISR) register. Clearing the bit
routes the interrupt to external interrupt 0, and setting the bit routes it to
external interrupt 1.
2.10.2 DMA and SCSI Interrupts
The SCSI core provides an interrupt output to indicate task completion
or an abnormal bus occurrence. The use of interrupts is optional and
may be disabled by resetting the appropriate bits in the
Mode (MR)
register ( 0xFC02 ) or the Select Enable (SER) register ( 0xFC04 ).
When an interrupt occurs, the Bus and Status (BSR) register and the
Current SCSI Bus Status (CSBS) register must be read to determine
which condition created the interrupt. The interrupt can be reset by
simply reading the
Reset Parity/Interrupt (RPI) register ( 0xFC07 ) or by
an external chip reset.
If the SCSI core has been properly initialized, an interrupt will be
generated in the following cases:
•
the chip is selected/reselected
•
a DMA transfer completes
•
a SCSI bus reset occurs
•
a parity error occurs during a data transfer
•
a bus phase mismatch occurs
•
a SCSI bus disconnection occurs
2.10.2.1 End of DMA Transfer Interrupt
The End of DMA bit determines when a block data transfer is complete.
Receive operations are complete when there is no data left in the SCSI
core and no additional handshakes occurring.