LSI Symbios SYM53C040, Technical Manual

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SFF-8067 Mode 3-21
DSK_WR/,
SEL_6 130/B9 When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to write data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045. Port 1 4 mA open drain
bidirectional
PARALLEL_
ESI/ 129/C9 Used to select between the SEL_ID
and the bidirectional interface. Pull-
up resistors on the interface are 3.3
k
Ω
ζ
minimum. When this pin is
asserted, the drive begins the
discovery process and prepares to
read or write data. When this pin is
deasserted, the drive is presented
with SEL_ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol.
Port 1 4 mA open drain
bidirectional
PA0 127/D9 This pin contains bit 0 of the
physical address of the enclosure. Port 0 Input
PA1 126/B10 This pin contains bit 1 of the
physical address of the enclosure. Port 0 Input
PA2 125/C10 This pin contains bit 2 of the
physical address of the enclosure. Port 0 Input
PA3 124/A11 This pin contains bit 3 of the
physical address of the enclosure. Port 0 Input
PA4 119/D10 This pin contains bit 4 of the
physical address of the enclosure. Port 0 Input
PA5 118/C12 This pin contains bit 5 of the
physical address of the enclosure. Port 0 Input
PA6 117/D11 This pin contains bit 6 of the
physical address of the enclosure. Port 0 Input
tied to V
DD
116/C13 – N/A Input
tied to V
DD
114/D12 – N/A Input
tied to V
DD
113/D3 – N/A Input
Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.)
Signal Name
Pin/Ball
No. Description 8067 Port
Pad
Configuration