LSI Symbios SYM53C040, Technical Manual

Page: 66 / 214

3-16 Signal Descriptions
3.1.3 JTAG Signals
Table 3.7 describes the signals for the JTAG Signals group.
Table 3.7 JTAG Signals
Pin
Name
Pin
Number
BGA Ball
Number Description Pad Type
Internal
Resistor
TCK 91 J13 Test Clock. The Test Clock pin
provides clocking for the JTAG test
logic and boundary scan. 5 V
tolerant
TTL input 100
µ
A
pull-up
TMS 90 J12 Test Mode Select. The Test Mode
Select pin receives a signal to
control the JTAG test operations and
boundary scans. 5 V
tolerant
TTL input 100
µ
A
pull-up
TDI 92 H10 Test Data In. The Test Data In pin
receives serial input data and
commands for JTAG test operations
and boundary scans. 5 V
tolerant
TTL input 100
µ
A
pull-up
TDO 89 J11 Test Data Out. The Test Data Out pin
provides serial output data for JTAG
test operations and boundary scans. 4 mA
Output None
TRST/ 151 C5 Test Reset. The Test Reset pin
receives a signal to reset the JTAG
TAP controller. It also simulates a
power-on reset for core logic (NOTE:
not JTAG compliant). 5 V
tolerant
TTL input 100
µ
A
pull-up