LSI Symbios SYM53C040, Technical Manual

Page: 82 / 214

4-10 SCSI and DMA Registers
SEL Select 1
DBP Data Bus Parity 0
Register: 0xFC04
Select Enable (SER)
Write Only
SE[7:0] Selection ID bits [7:0]
The Select Enable register is a write only register that is
used as a mask to monitor a single ID during a selection
attempt. The simultaneous occurrence of the
corresponding ID bit, BSY/ false and SEL/ true will cause
an interrupt. This interrupt can be disabled by resetting all
bits in this register and in the
Select Enable High (SENHI)
register ( 0xFC0C ). If the Enable Parity Checking bit
(register 0xFC02, bit 5) is active (1), parity will be
checked during selection.
Register: 0xFC05
Bus and Status (BSR)
Read Only
The Bus and Status register is a read only register that can be used to
monitor the remaining SCSI control signals not found in the
Current SCSI
Bus Status (CSBS) register (ATN/ and ACK/), as well as six other status
bits.
EOD End of DMA Transfer 7
The End of DMA Transfer bit is set when a DMA transfer
completes. The REQ/ and ACK/ signals should be
monitored to ensure that the last byte has been
7 0
SE[7:0]
Defaults:
x x x x x x x x
7 6 5 4 3 2 1 0
EOD R PERR IRA PMATCH BERR ATN ACK
Defaults:
0 0 0 0 x 0 SATN/ SACK/