20
LatticeXP2 Advanced
Lattice Semiconductor
Evaluation Board User’s Guide
Table 28. PCI Connector Component Side
J11 Pin#
Signal
I/O
Description
LatticeXP2 Connection
1
12V
Vcc
12V voltage supply pin
—
2
TCK
-
PCI JTAG TCK signal
—
3
GND
Vss
System ground
GND
4
TDO
-
JTAG TDO signal
—
5
5V
Vcc
5V voltage supply pin
—
6
5V
Vcc
5V voltage supply pin
—
7
INTB#
O
PCI INTB# signal
—
8
INTD#
O
PCI INTD# signal
—
9
PRSNT1#
O
PCI PRSNT1# signal
—
10
Reserved
-
Reserved
—
11
PRSNT2#
O
PCI PRSNT2# signal
—
14
Reserved
-
Reserved
—
15
GND
Vss
System ground
GND
16
CLK
I
PCI system clock
AB14
17
GND
Vss
System ground
GND
18
REQ#
O
PCI arbitration request signal
W5
19
+VIO
Vio
VIO voltage supply pin
—
20
AD[31]
I/O
PCI address and bit 31
Y5
21
AD[29]
I/O
PCI address and data bit 29
Y6
22
GND
Vss
System ground
GND
23
AD[27]
I/O
PCI address and data bit 27
AB6
24
AD[25]
I/O
PCI address and data bit 25
AA7
25
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
26
C/BE#[3]
I/O
PCI bus command, byte enable, bit 3
Y8
27
AD[23]
I/O
PCI address and data bit 23
W4
28
GND
Vss
System ground
GND
29
AD[21]
I/O
PCI address and data bit 21
W6
30
AD[19]
I/O
PCI address and data bit 19
U8
31
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
32
AD[17]
I/O
PCI address and data bit 17
W8
33
C/BE#[2]
I/O
PCI bus command, byte enable, bit 2
V9
34
GND
Vss
System ground
GND
35
IRDY#
I/O
PCI initiator ready signal
T10
36
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
37
DEVSEL#
I/O
PCI device select
T9
38
GND
Vss
System ground
GND
39
LOCK#
I/O
PCI lock signal
-
40
PERR#
I/O
PCI parity error signal
V10
41
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
42
SERR#
I/O
PCI system error signal
V11
43
+3.3V
Vcc
3.3V voltage supply pin
+3.3V
44
C/BE#[1]
I/O
PCI bus command, byte enable, bit 1
T12
45
AD[14]
I/O
PCI address and data bit 14
T13
46
GND
Vss
System ground
GND
