36
LatticeXP2 Advanced
Lattice Semiconductor
Evaluation Board User’s Guide
Figure 21.
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
VC
C
_
3
.3
V
LV
_C
T
S_N
LV
_R
T
S_N
LV
_T
X
D
LV
_R
X
D
HV
_
R
X
D
HV
_
TX
D
H
V
_R
T
S_N
HV
_
C
TS
_
N
R
S232_C
T
S_N
R
S232_0
R
S232_R
X
D
R
S232_1
R
S232_T
X
D
R
S232_2
R
S232_R
T
S_N
R
S232_3
US
B
0
US
B
_
V
P
US
B
2
US
B
_
R
C
V
US
B
5
US
B
_
O
E
_
N
US
B
1
US
B
_
V
M
U
SB3
U
SB_SU
S
U
SB4
U
SB_SP
D
VC
C
_
3
.3
V
OSC
_P
C
LK
VC
C
_
3
.3
V
OSC
_P
LLC
LK
A_I
N
1
IDC1
3
A_I
N
0
IDC1
2
A_OU
T
0
IDC1
6
A_OU
T
1
IDC1
7
A_OU
T
3
IDC1
9
A_OU
T
2
IDC1
8
A_I
N
2
IDC1
4
A_I
N
3
IDC1
5
IDC[0
..1
0
]
XP2
_
N
5
ID
C
5
XP2
_
N
6
ID
C
6
XP2
_
N
2
ID
C
8
XP2
_
M
3
ID
C
7
XP2
_
M
7
ID
C
1
0
XP2
_
M
6
ID
C
9
XP2
_
P7
ID
C
2
XP2
_
N
7
ID
C
1
XP2
_
V1
ID
C
3
XP2
_
W
1
ID
C
4
XP2
_
E
4
ID
C
0
IDC1
1
XP2
_
F
6
VC
C
_
3
.3
V
V
C
C
_
3.
3V
IDC2
0
XO
_
K
5
IDC2
1
XO
_
K
4
IDC2
2
XO
_
M
5
IDC2
3
XO
_
M
4
ID
C
[12.
.23]
TP
_
X
O
_
K
5
TP
_
X
O
_
K
4
TP
_
X
O
_
M
5
TP
_
X
O
_
M
4
TP
_
X
P
2
_
E
4
TP
_
X
P
2
_
N
7
TP
_
X
P
2
_
P
7
TP
_
X
P
2
_
V
1
TP
_
X
P
2
_
W
1
TP
_
X
P
2
_
N
5
TP
_
X
P
2
_
N
6
TP
_
X
P
2
_
M
3
TP
_
X
P
2
_
N
2
TP
_
X
P
2
_
M
6
TP
_
X
P
2
_
M
7
TP
_
X
P
2
_
F
6
R
S
232_[
0.
.3]
US
B
[0
..
5
]
VC
C
_
3
.3
V
VC
C
_
5
.0
V
OSC
_P
LLC
LK
OSC
_P
C
LK
IDC[0
..1
0
]
IDC[1
2
..2
3
]
XP2
_
F
6
Ti
tl
e
Siz
e
D
o
c
u
m
e
nt
N
u
m
b
er
Re
v
D
at
e:
Sheet
of
B
OSC
, U
SB & R
S-
2
32
C
31
4
Ti
tl
e
Siz
e
D
o
c
u
m
e
nt
N
u
m
b
er
R
ev
D
at
e:
Sheet
of
B
OSC
, U
SB & R
S-
2
32
C
31
4
Ti
tl
e
Siz
e
D
o
c
u
m
e
nt
N
u
m
b
er
R
ev
D
at
e:
Sheet
of
B
OSC
, U
SB & R
S-
2
32
C
31
4
Used when the FPGA is
configured as USB host.
Used when the FPGA is
configured as USB device.
Wired as USB Host ->
installed Jumpers on pin 1-2 of all headers
Wired as USB Device ->
installed Jumpers on pin 2-3 of all headers
TXD Selection
RXD Selection
/CTS Selection
/RTS Selection
Wired as DCE (default) ->
installed Jumpers on pin 1-2 of all headers
Wired as DTE ->
installed Jumpers on pin 2-3 of all headers
Lattice Semiconductor Corporation
[2]
[2]
[12]
RS-232
USB(Type B)
USB(Type A)
(Female)
[13]
OSC1(L4)
OSC2(A2)
Oscillator Socket
(33.33 MHz OSC Installed)
[6]
[2]
[2]
[8]
Place these resistors near the FPGA
Place these resistors near the FPGA
[2]
ADCs, DACs, XO Test Points
XP2 Test Points
Place these resistors
near the IDC connector
Place these resistors
near the IDC connector
For high speed signals over ribbon cable:
TX - install series resistors of 33 ohms near the F
PGA and
70 ohms near the IDC connector. Do not install resi
stors
tied to VCC_3.3v or GND.
RX - series resistors remain 0 ohm. Resistors tied
to
VCC_3.3v and GND should be 240 ohms each.
[8]
R2
1
DN
L
R2
1
DN
L
J1
IDC2
4
J1
IDC2
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
J2
2
HE
A
D
E
R
3
J2
2
HE
A
D
E
R
3
1
2
3
J2
7
HE
A
D
E
R
3
J2
7
HE
A
D
E
R
3
1
2
3
R1
6
5
3
3
R1
6
5
3
3
C1
0
0
0.
1uF
0402
C1
0
0
0.
1uF
0402
R1
7
4
0
R1
7
4
0
C6
8
4.
7uF
C
eram
ic
X
5
R
0603
C6
8
4.
7uF
C
eram
ic
X
5
R
0603
1
2
R1
5
0
0
R1
5
0
0
R1
6
2
DN
L
R1
6
2
DN
L
R3
6
15K
R3
6
15K
R1
7
5
0
R1
7
5
0
R1
5
3
DN
L
R1
5
3
DN
L
1
2
4
3
J2
0
U
S
B Ser
ies
-B R
ec
ept
ac
le
M
o
lex
67068-8000
1
2
4
3
J2
0
U
S
B Ser
ies
-B R
ec
ept
ac
le
M
o
lex
67068-8000
VBU
S
1
D-
2
D+
3
GN
D
4
5
MH1
6
MH2
R1
7
7
0
R1
7
7
0
R1
6
0
DN
L
R1
6
0
DN
L
R3
5
15K
R3
5
15K
R7
9
0
R7
9
0
R1
7
9
0
R1
7
9
0
R1
4
9
0
R1
4
9
0
R1
5
2
DN
L
R1
5
2
DN
L
C6
9
1uF
C
e
ram
ic
X
5
R
0402
C6
9
1uF
C
e
ram
ic
X
5
R
0402
1
2
R7
3
0
R7
3
0
J3
0
HE
A
D
E
R
3
J3
0
HE
A
D
E
R
3
1
2
3
R1
4
5
0
R1
4
5
0
R1
5
4
DN
L
R1
5
4
DN
L
Y1
DIP
S
O
C
-8
x2
Y1
DIP
S
O
C
-8
x2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R1
7
1
0
R1
7
1
0
R8
0
0
R8
0
0
R7
4
0
R7
4
0
R1
4
4
0
R1
4
4
0
R1
5
5
DN
L
R1
5
5
DN
L
R2
7
DN
L
R2
7
DN
L
R6
9
DN
L
R6
9
DN
L
R1
4
1
0
R1
4
1
0
C1
0
1
0.
1uF
0402
C1
0
1
0.
1uF
0402
R1
7
2
0
R1
7
2
0
J2
1
HE
A
D
E
R
3
J2
1
HE
A
D
E
R
3
1
2
3
R7
5
0
R7
5
0
R1
4
8
0
R1
4
8
0
R1
4
3
0
R1
4
3
0
R1
6
1
DN
L
R1
6
1
DN
L
R1
8
DN
L
R1
8
DN
L
R7
1
DN
L
R7
1
DN
L
C9
7
0.
1uF
0402
C9
7
0.
1uF
0402
R1
4
0
0
R1
4
0
0
R1
7
0
0
R1
7
0
0
R1
3
7
0
R1
3
7
0
R7
6
0
R7
6
0
J2
3
HE
A
D
E
R
3
J2
3
HE
A
D
E
R
3
1
2
3
R2
0
DN
L
R2
0
DN
L
R1
4
2
0
R1
4
2
0
R1
6
3
DN
L
R1
6
3
DN
L
R2
5
DN
L
R2
5
DN
L
C9
9
0.
1uF
0402
C9
9
0.
1uF
0402
R1
3
9
0
R1
3
9
0
R1
6
4
3
3
R1
6
4
3
3
R7
0
DN
L
R7
0
DN
L
R1
6
9
0
R1
6
9
0
R1
8
0
DN
L
R1
8
0
DN
L
R1
3
6
0
R1
3
6
0
U7
M
AX
3232
TS
S
O
P
1
6
U7
M
AX
3232
TS
S
O
P
1
6
GN
D
15
VC
C
16
R1
IN
13
R2
IN
8
T2
IN
10
T1
IN
11
C1
+
1
C1
-
3
C2
+
4
C2
-
5
R1
O
UT
12
R2
O
UT
9
T1
O
U
T
14
T2
O
U
T
7
V+
2
V-
6
R2
6
DN
L
R2
6
DN
L
J2
9
HE
A
D
E
R
3
J2
9
HE
A
D
E
R
3
1
2
3
C9
8
0.
1uF
0402
C9
8
0.
1uF
0402
R1
5
9
DN
L
R1
5
9
DN
L
R1
7
DN
L
R1
7
DN
L
R1
3
8
0
R1
3
8
0
R1
6
8
0
R1
6
8
0
C7
0
1uF
C
e
ram
ic
X
5
R
0402
C7
0
1uF
C
e
ram
ic
X
5
R
0402
1
2
R1
3
5
0
R1
3
5
0
R1
8
1
DN
L
R1
8
1
DN
L
J2
8
HE
A
D
E
R
3
J2
8
HE
A
D
E
R
3
1
2
3
MAX3454EETE (or NCN2500MNR2)
U4
M
AX
3454EET
E
QF
N
1
6
MAX3454EETE (or NCN2500MNR2)
U4
M
AX
3454EET
E
QF
N
1
6
NC (
E
N_
RP
U)
16
N
C
(
E
N
_Vo
bus
#)
5
VL (Vcc
)
15
NC
8
VT
R
M
(
V
re
g)
12
VBU
S
(
V
us
b)
14
D+
11
D-
10
GN
D
6
VP
3
VM
4
RCV
2
SU
S (
SPN
D
)
7
SPD
(
D
SPD
)
1
OE#
9
EN
U
M
(
VObus
)
13
R2
8
DN
L
R2
8
DN
L
J1
0
IDC2
4
J1
0
IDC2
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R1
9
DN
L
R1
9
DN
L
R1
5
8
DN
L
R1
5
8
DN
L
R1
7
8
0
R1
7
8
0
R6
8
DN
L
R6
8
DN
L
R1
8
3
DN
L
R1
8
3
DN
L
R1
3
4
0
R1
3
4
0
R7
2
0
R7
2
0
R2
4
DN
L
R2
4
DN
L
R7
8
0
R7
8
0
R1
5
1
0
R1
5
1
0
1
2
3
4
J1
6
U
S
B Series
-A R
ec
ept
ac
le M
o
lex
67643-2910
1
2
3
4
J1
6
U
S
B Series
-A R
ec
ept
ac
le M
o
lex
67643-2910
VBU
S
1
D-
2
D+
3
GN
D
4
MH1
5
MH2
6
R1
5
7
DN
L
R1
5
7
DN
L
R1
7
6
0
R1
7
6
0
J2
6
C
O
N
N
EC
T
O
R
D
B
9 N
o
rc
om
p 182-009-212-161
J2
6
C
O
N
N
EC
T
O
R
D
B
9 N
o
rc
om
p 182-009-212-161
5
9
4
8
3
7
2
6
1
10
11
R2
3
DN
L
R2
3
DN
L
R1
8
2
DN
L
R1
8
2
DN
L
R1
5
6
DN
L
R1
5
6
DN
L
R2
2
DN
L
R2
2
DN
L
J2
4
H
EAD
ER
3
J2
4
H
EAD
ER
3
1
2
3
R1
6
7
0
R1
6
7
0
OSC, LSB and RS-232
