18
LatticeXP2 Advanced
Lattice Semiconductor
Evaluation Board User’s Guide
Ethernet PHY
In the upper middle portion of the board is U11, a National Semiconductor Gigabit Ethernet PHY (DP83865). The
LatticeXP2 FPGA interacts with the PHY over a Media Independent Interface (MII). The PHY is connected to an
RJ45 connector J43 on the Media Dependent Interface (MDI). The RJ45 connector J43 has built in magnetics and
spark-gap capacitor.
The PHY is available on the board in order to demonstrate the Lattice Ethernet Media Access (MAC) IP core. How-
ever, it is also possible to use the PHY to evaluate a custom MAC solution.
Refer to the schematic and the National Semiconductor DP83865 Data Sheet for detailed information about the
operation of the Ethernet PHY interface on this device. Refer to Table 27 for a description of the Ethernet PHY con-
nections.
DDR2_A6
R16
3
94
DDR2_A7
T17
3
92
DDR2_A8
Y20
3
93
DDR2_A9
Y19
3
91
DDR2_A10
W22
3
105
DDR2_A11
G15
2
90
DDR2_A12
G16
2
89
DDR2_A13
F17
2
116
DDR_BA0
P20
3
107
DDR_BA1
P22
3
106
DDR_BA2
F18
2
85
DDR2_CK0_P
G17
2
30
DDR2_CK0_N
H18
2
32
DDR2_CK1_P
B21
2
164
DDR2_CK1_N
C21
2
166
DDR2_CKE0
J19
2
79
DDR2_CKE1
C20
2
80
DDR2_S0_N
J18
2
110
DDR2_S1_N
H16
2
115
DDR2_RAS_N
K16
2
108
DDR2_CAS_N
L18
2
113
DDR2_WE_N
L19
2
109
DDR2_ODT0
P18
3
114
DDR2_ODT1
N18
3
119
DDR2_SDA
AA2
0
195
DDR2_SCL
Y2
0
197
Table 26. DDR2 Interface to SODIMM Socket (Continued)
Description
LatticeXP2 I/O
sysIO Bank
J36
