16
LatticeXP2 Advanced
Lattice Semiconductor
Evaluation Board User’s Guide
PS/2 Mouse
The PS/2 mouse connector (JP1) on this board connects the clock and data through the PCA9306 level translator
to the LatticeXP2. The clock and data are connected as described in Table 24.
Table 24. Connections Between PS/2 Mouse Connector and LatticeXP2
JP1 Pin #
Signal
LatticeXP2 I/O
Description
1
DATA
V5
PS/2 data signal, open drain
5
CLOCK
V4
PS/2 clock signal, open drain
RS-232
The RS-232 interface on this board includes a RS-232 interface chip (MAX3232), a 9-pin D-sub female connector
and four headers. This RS-232 interface can be configured to DCE or DTE by changing the jumper settings of J27,
J28, J29 and J30 headers. These headers are used to connect the MAX3232 to the D-sub connector. Installing
jumpers on Pin 1 and Pin 2 of these headers configures the RS-232 to DCE. Installing jumpers on Pin 2 and Pin 3
of these headers configures the RS-232 to DTE. The connections and functions of the signals between MAX3232
and LatticeXP2 stay the same for DCE and DTE configurations. These are listed in Table 25.
Table 25.
Signal Name
MAX3232 Pin
LatticeXP2 I/O
LatticeXP2 Bank
LatticeXP2 I/O Type
/CTS
9 (R2OUT)
C3
7
Input
RXD
12 (R1OUT)
B2
7
Input
TXD
11 (T1IN)
B1
7
Output
/RTS
10 (T2IN)
C2
7
Output
Connections Between MAX3232 and LatticeXP2
DDR2
The 200-pin SODIMM socket provides a built-in 32-bit interface to standard 1.8V DDR2 SDRAM memory modules
(PC2-5300). Lattice recommends the Kingston KVR533D284/512. However, other memories conforming to this
standard will also work. The required V
REF
and V
TT
voltages, as well as termination of each signal to V
TT
are pro-
vided. Performance has been verified at above the 533Mbps data rate. Write mode dynamic ODT at the memory
modules is fully supported, while read mode ODT at the controller (FPGA) is approximated with external termina-
tions optimized for best performance. The connections between the connector pins and LatticeXP2 balls are shown
in Table 26.
13
ENUM
Vobus
—
Connect to J21 pin 2
14
Vbus
Vusb
—
Connect to USB connectors
15
VL
Vcc
—
Connect to 3.3V
16
NC
EN_RPU
—
Connect to J21 pin 2
Table 26. DDR2 Interface to SODIMM Socket
Description
LatticeXP2 I/O
sysIO Bank
J36
DDR2_DQ0
R21
3
5
DDR2_DQ1
R20
3
7
DDR2_DQ2
N17
3
17
DDR2_DQ3
N16
3
19
DDR2_DQ4
P19
3
4
DDR2_DQ5
R19
3
6
Table 23. Connections Between USB 1.1 Transceiver and LatticeXP2 (Continued)
Pin #
MAX3454EETE NCN2500MNR2
LatticeXP2 I/O
Description
