Lattice Semiconductor MachXO5-NX Development Kit, User Manual

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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34 FPGA-EB-02052-0.90
9.2. General Purpose Push Buttons
The MachXO5-NX Development Board provides four push button switches, SW2, SW3, SW4 and SW5, for demos and
user applications. Pressing these buttons drives a logic level 0 to the corresponding I/O pins.
Table 9.2. Push Button Switch Signals
Push Button Ref Name Net Name MachXO5-25 Ball Location Test Points
SW2 PB1 E19 TP3
SW3 PB2 F20 TP4
SW4 PB3 B7 Pin 2 of JP4
SW5 PB4 G20 Pin 2 of JP5
SW2 and SW3 are designed for general-purpose applications. SW4 and SW5 are designed with additional jumper JP4
and JP5. SW4 can be used as ASC global reset push button when JP4 is set to connect with EXPCON_IO20, which is
connect to MANDATORY_RESET signal when mated with Lattice ASC Bridge Board. Refer to
ASC Bridge Board
Evaluation Board User Guide (FPGA-EB-02025) for detailed information with ASC application. SW5 can be used as
PROGRAMN push button when JP5 is set to trigger the configuration process without power cycle. For detailed
information on PROGRAMN, refer to MachXO5 Programming and Configuration User Guide (FPGA-TN-02271).
9.3. General Purpose LEDs
The MachXO5-NX Development Board provides eight red LEDs that are connected to I/O within Bank 5. The LEDs are
lighted when the output is driven LOW.
Table 9.3 lists the red LEDs and their associated pins.
Table 9.3. LED Signals
Red LEDs Ref Name Net Name MachXO5-25 Ball Location
D1 XLED0 R3
D2 XLED1 R2
D3 XLED2 R1
D4 XLED3 P7
D5 XLED4 H12
D6 XLED5 H11
D7 XLED6 G13
D8 XLED7 G12
9.4. Seven-Segment Display
The MachXO5-NX Development Board features a blue Seven-segment Display of D20, as shown in Figure 9.3 , controlled
by I/O within Bank 5. Each segment LED is lighted blue when the output is driven LOW. Table 9.4 lists the connections
between display LED segments and their associated driver pins.
Figure 9.3. Seven-Segment Display and its Symbol